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參數(shù)資料
| 型號(hào)： | 3D7225 |
| 廠商： | Data Delay Devices, Inc. |
| 英文描述： | MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7225) |
| 中文描述： | 整體式5 - TAP在固定延遲線（系列3D7225） |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大?。?/td> | 136K |
| 代理商： | 3D7225 |
Doc #05002
4/15/05
3D7225
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
3
APPLICATION NOTES (CONT’D)
custom reference designator identifying the
intended frequency and duty cycle of operation.
The programmed delay accuracy of the device is
guaranteed, therefore, only for the user specified
input characteristics. Small input pulse width
variation about the selected pulse width will only
marginally impact the programmed delay
accuracy, if at all. Nevertheless, it is strongly
recommended that the engineering staff at DATA
DELAY DEVICES be consulted.
POWER SUPPLY AND
TEMPERATURE CONSIDERATIONS
The delay of CMOS integrated circuits is strongly
dependent on power supply and temperature.
The monolithic 3D7225 programmable delay line
utilizes novel and innovative compensation
circuitry to minimize the delay variations induced
by fluctuations in power supply and/or
temperature.
The thermal coefficient is reduced to 250 PPM/C,
which is equivalent to a variation, over the -40C
to 85C operating range, of
±
2% from the room-
temperature delay settings and/or
1.0ns,
whichever is greater. The power supply
coefficient is reduced, over the 4.75V-5.25V
operating range, to
±
1% of the delay settings at
the nominal 5.0VDC power supply and/or
1.0ns,
whichever is greater.
It is essential that the
power supply pin be
adequately bypassed
and filtered. In addition, the power bus
should be of as low an impedance
construction as possible. Power planes are
preferred.
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
DC Supply Voltage
V
DD
Input Pin Voltage
V
IN
Input Pin Current
I
IN
Storage Temperature
T
STRG
Lead Temperature
T
LEAD
MIN
-0.3
-0.3
-1.0
-55
MAX
7.0
V
DD
+0.3
1.0
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(-40C to 85C, 4.75V to 5.25V)
PARAMETER
SYMBOL
Static Supply Current*
I
DD
High Level Input Voltage
V
IH
Low Level Input Voltage
V
IL
High Level Input Current
I
IH
Low Level Input Current
I
IL
High Level Output
Current
Low Level Output Current
I
OL
MIN
2.0
TYP
3.5
-35.0
MAX
5.5
0.8
1.0
1.0
-4.0
UNITS
mA
V
V
μ
A
μ
A
mA
NOTES
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
I
OH
4.0
15.0
mA
Output Rise & Fall Time
T
R
& T
F
2.0
2.5
ns
*I
(Dynamic) = 5 * C
* V
* F
where: C
LD
= Average capacitance load/tap (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7225-.75 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7225) |
| 3D7225-1 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7225) |
| 3D7225-1.5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7225) |
| 3D7225-10 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7225) |
| 3D7225-100 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 5-TAP FIXED DELAY LINE (SERIES 3D7225) |
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