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參數(shù)資料
| 型號： | 3D7304D-10 |
| 廠商： | DATA DELAY DEVICES INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | MONOLITHIC QUADRUPLE FIXED DELAY LINE |
| 中文描述： | SILICON DELAY LINE, TRUE OUTPUT, PDSO14 |
| 封裝： | 0.150 INCH, SOIC-14 |
| 文件頁數(shù)： | 4/4頁 |
| 文件大小： | 40K |
| 代理商： | 3D7304D-10 |
3D7304
Doc #96002
12/2/96
DATA DELAY DEVICES, INC.
4
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT:
Ambient Temperature:
25
o
C
±
3
o
C
Supply Voltage (Vcc):
5.0V
±
0.1V
Input Pulse:
OUTPUT:
R
load
:
C
load
:
Threshold:
10K
±
10%
5pf
±
10%
1.5V (Rising & Falling)
High = 3.0V
±
0.1V
Low = 0.0V
±
0.1V
50
Max.
3.0 ns Max. (measured
between 0.6V and 2.4V )
PW
IN
= 1.25 x Total Delay
PER
IN
= 2.5 x Total Delay
Source Impedance:
Rise/Fall Time:
Pulse Width:
Period:
NOTE:
The above conditions are for test only and do not in any way restrict the operation of the device.
10K
470
5pf
Device
Under
Test
Digital
Scope
OUT1
OUT2
OUT3
OUT4
OUT
TRIG
IN
REF
TRIG
Figure 2: Test Setup
DEVICE UNDER
TEST (DUT)
DIGITAL SCOPE/
TIME INTERVAL COUNTER
PULSE
GENERATOR
IN4
COMPUTER
SYSTEM
PRINTER
IN3
IN2
IN1
Figure 3: Timing Diagram
t
PLH
t
PHL
PER
IN
PW
IN
t
RISE
t
FALL
0.6V
0.6V
2.4V
1.5V
1.5V
1.5V
V
IH
V
IL
V
OH
V
OL
INPUT
SIGNAL
OUTPUT
SIGNAL
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