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參數(shù)資料
| 型號(hào)： | 3D7408-0.5 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 中文描述： | 整體式8位可編程延遲線(xiàn) |
| 文件頁(yè)數(shù)： | 6/7頁(yè) |
| 文件大?。?/td> | 65K |
| 代理商： | 3D7408-0.5 |
3D7408
Doc #96003
12/2/96
DATA DELAY DEVICES, INC.
6
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
DEVICE SPECIFICATIONS
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Supply Voltage
Input Pin Voltage
Input Pin Current
Storage Temperature
Lead Temperature
SYMBOL
V
DD
V
IN
I
IN
T
STRG
T
LEAD
MIN
-0.3
-0.3
-10
-55
MAX
7.0
V
DD
+0.3
10
150
300
UNITS
V
V
mA
C
C
NOTES
25C
10 sec
TABLE 4: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
SYMBOL
I
DD
V
IH
V
IL
I
IH
I
IL
I
OH
MIN
MAX
40
UNITS
mA
V
V
μ
A
μ
A
mA
NOTES
2.0
0.8
1.0
1.0
V
IH
= V
DD
V
IL
= 0V
V
DD
= 4.75V
V
OH
= 2.4V
V
DD
= 4.75V
V
OL
= 0.4V
C
LD
= 5 pf
-4.0
Low Level Output Current
I
OL
4.0
mA
Output Rise & Fall Time
T
R
& T
F
2
ns
*I
(Dynamic) = C
* V
* F
where:
C
LD
= Average capacitance load/line (pf)
F = Input frequency (GHz)
Input Capacitance = 10 pf typical
Output Load Capacitance (C
LD
) = 25 pf max
TABLE 5: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Clock Frequency
Enable Width
Clock Width
Data Setup to Clock
Data Hold from Clock
Data Setup to Enable
Data Hold from Enable
Enable to Serial Output Valid
Enable to Serial Output High-Z
Clock to Serial Output Valid
Clock to Serial Output Invalid
Enable Setup to Clock
Enable Hold from Clock
Parallel Input Valid to Delay Valid
Parallel Input Change to Delay Invalid
Enable to Delay Valid
Enable to Delay Invalid
Input Pulse Width
Input Period
Input to Output Delay
SYMBOL
f
C
t
EW
t
CW
t
DSC
t
DHC
t
DSE
t
DHE
t
EQV
t
EQZ
t
CQV
t
CQX
t
ES
t
EH
t
PDV
t
PDX
t
EDV
t
EDX
t
WI
Period
t
PLH
, t
PHL
MIN
TYP
MAX
80
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
10
10
10
3
10
3
20
20
20
10
10
10
20
40
1
1
1
1
0
35
45
0
8
20
% of Total Delay
% of Total Delay
ns
See Table 1
See Table 1
See Table 2
NOTES: 1 -
Refer to
PROGRAMMED DELAY (ADDRESS) UPDATE
section
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 3D7408-5 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-4 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-3 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-2 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-1 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7408-1 | 制造商:DATADELAY 制造商全稱(chēng):Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-2 | 制造商:DATADELAY 制造商全稱(chēng):Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-3 | 制造商:DATADELAY 制造商全稱(chēng):Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-4 | 制造商:DATADELAY 制造商全稱(chēng):Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-5 | 制造商:DATADELAY 制造商全稱(chēng):Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
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