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參數(shù)資料
| 型號： | 3D7408-3 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 中文描述： | 整體式8位可編程延遲線 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 65K |
| 代理商： | 3D7408-3 |
3D7408
Doc #96003
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
1
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7408)
FEATURES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Increment range:
0.25 through 5.0ns
Delay tolerance:
1% (See Table 1)
Temperature stability:
±
3% typical (0C-70C)
Vdd stability:
±
1% typical (4.75V-5.25V)
Minimum input pulse width:
10% of total
delay
Programmable via 3-wire serial or 8-bit
parallel interface
FUNCTIONAL DESCRIPTION
The 3D7408 Programmable 8-Bit Silicon Delay Line product
family consists of 8-bit, user-programmable CMOS silicon
integrated circuits. Delay values, programmed either via the
serial or parallel interface, can be varied over 255 equal steps
ranging from 250ps to 5.0ns inclusively. Units have a typical
inherent (zero step) delay of 12ns to 17ns (See Table 1). The
input is reproduced at the output without inversion, shifted in time
as per user selection. The 3D7408 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features
both rising- and falling-edge accuracy.
The all-CMOS 3D7408 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving
surface mount 16-pin SOIC.
PACKAGES
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
IN
AE
SO/P0
P1
P2
P3
P4
GND
VDD
OUT
MD
P7
P6
SC
P5
SI
3D7408
3D7408G Gull Wing
(300 Mil)
DIP
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
AE
SO/P0
P1
P2
P3
P4
GND
VDD
OUT
MD
P7
P6
SC
P5
SI
3D7408S
SOIC
(300 Mil)
data
delay
devices,
inc.
3
(For mechanical data, see Case Dimensions document)
PIN DESCRIPTIONS
IN
OUT
MD
AE
P0-P7 Parallel Data Input
SC
Serial Clock
SI
Serial Data Input
SO
Serial Data Output
VCC
+5 Volts
GND
Ground
Signal Input
Signal Output
Mode Select
Address Enable
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
DELAYS AND TOLERANCES
Step 0
Delay (ns)
Delay (ns)
12
±
2
75.75
±
4.0
12
±
2
139.5
±
4.0
12
±
2
267.0
±
5.0
14
±
2
522.0
±
6.0
17
±
2
782.0
±
8.0
17
±
2
1037
±
9.0
17
±
2
1292
±
10
INPUT RESTRICTIONS
Absolute Max
Oper Freq
90 MHz
45 MHz
22 MHz
11 MHz
7.5 MHz
5.5 MHz
4.4 MHz
Step 255
Delay
Increment (ns)
0.25
±
0.15
0.50
±
0.25
1.00
±
0.50
2.00
±
1.00
3.00
±
1.50
4.00
±
2.00
5.00
±
2.50
Max Operating
Frequency
6.25 MHz
3.15 MHz
1.56 MHz
0.78 MHz
0.52 MHz
0.39 MHz
0.31 MHz
Min Operating
P.W.
Absolute Min
Oper P.W.
3D7408-0.25
3D7408-0.5
3D7408-1
3D7408-2
3D7408-3
3D7408-4
3D7408-5
80.0 ns
160.0 ns
320.0 ns
640.0 ns
960.0 ns
1280.0 ns
1600.0 ns
5.5 ns
11.0 ns
22.0 ns
44.0 ns
66.0 ns
88.0 ns
110.0 ns
NOTES: Any delay increment between 0.25 and 5.0 ns not shown is also available.
All delays referenced to input pin
1996 Data Delay Devices
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 3D7408-2 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-1 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7418-0.25 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 - LOW NOISE) |
| 3D7424D-2 | MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE |
| 3D7428-10 | MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 3D7408-4 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408-5 | 制造商:DATADELAY 制造商全稱:Data Delay Devices, Inc. 功能描述:MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE |
| 3D7408G0.25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7408G0.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| 3D7408G1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
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