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參數(shù)資料
| 型號(hào)： | 4015B |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output |
| 中文描述： | CMOS雙4級(jí)靜態(tài)移位寄存器在串行輸入/并行輸出 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大小： | 118K |
| 代理商： | 4015B |
7-89
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4015BMS
CMOS Dual 4-Stage Static Shift Register
With Serial Input/Parallel Output
Pinout
CD4015BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CLOCK B
Q4B
Q3A
Q2A
Q1A
RESET A
VSS
DATA A
VDD
RESET B
Q1B
Q2B
Q3B
Q4A
CLOCK A
DATA B
DATA A
CLOCK A
RESET A
DATA B
CLOCK B
RESET B
Q1A
Q2A
Q3A
Q4A
Q1B
Q2B
Q3B
Q4B
VSS
VDD
7
9
6
15
1
14
5
4
3
10
13
12
11
2
16
8
4
STAGE
4
STAGE
Features
High-Voltage Type (20V Rating)
Medium Speed Operation 12MHz (typ.) Clock Rate at
VDD - VSS = 10V
Fully Static Operation
8 Master-Slave Flip-Flops Plus Input and Output Buffering
100% Tested For Quiescent Current at 20V
5V, 10V and 15V Parametric Ratings
Standardized Symmetrical Output Characteristics
Maximum Input Current of 1
A at 18V Over Full Pack-
age-Temperature Range; 100nA at 18V and 25oC
Noise Margin (Full Package-Temperature Range) =
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specications for Description of
‘B’ Series CMOS Devices”
Applications
Serial-Input/Parallel-Output Data Queueing
Serial to Parallel Data Conversion
General-Purpose Register
Description
CD4015BMS consists of two identical, independent, 4-stage
serial-input/parallel output registers. Each register has inde-
pendent CLOCK and RESET inputs as well as a single serial
DATA input. “Q” outputs are available from each of the four
stages on both registers. All register stages are D type, mas-
ter-slave ip-ops. The logic level present at the DATA input
is transferred into the rst register stage and shifted over one
stage at each positive-going clock transition. Resetting of all
stages is accomplished by a high level on the reset line.
Register expansion to 8 stages using one CD4015BMS
package, or to more than 8 stages using additional
CD4015BMS’s is possible.
The CD4015BMS is supplied in these 16 lead outline pack-
ages:
Braze Seal DIP
H4X
Frit Seal DIP
H1F
Ceramic Flatpack
H6W
December 1992
File Number
3295
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