參數(shù)資料
型號: 4015B
廠商: Intersil Corporation
英文描述: CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output
中文描述: CMOS雙4級靜態(tài)移位寄存器在串行輸入/并行輸出
文件頁數(shù): 8/8頁
文件大?。?/td> 118K
代理商: 4015B
7-96
CD4015BMS
Chip Dimensions and Pad Layout
FIGURE 8.
TYPICAL POWER DISSIPATION AS
A FUNCTION OF FREQUENCY
Typical Performance Characteristics (Continued)
CL = 50pF
CL = 15pF
AMBIENT TEMPERATURE (TA) = +25
oC
SUPPLY VOLTAGE (VDD) = 15V
10V
5V
10V
tr, tf = 20ns
RL = 200k
1
24 6 8
10
24 6 8
102
24 6 8
103
24
6 8
104
24 6 8
CLOCK INPUT FREQUENCY (fCL) (kHz)
105
10
102
2
8
6
4
103
2
8
6
4
104
2
8
6
4
105
2
8
6
4
POWER
DISSIP
A
TION
(PD)
(
W)
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10-3 inch)
METALLIZATION: Thickness: 11k
14k, AL.
PASSIVATION: 10.4k - 15.6k
, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
DIE SIZE: X = 80 (77 - 85) = (1.956 - 2.159)
Y = 98 (95 - 103) = (2.413 - 2.616)
13
3
14
15
12
11
10
2
1
16
4
5
6
7
8
9
98
80
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