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參數(shù)資料
| 型號(hào)： | 4LVC652PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal transceiver/register with dual enable 3-State |
| 中文描述： | LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 147K |
| 代理商： | 4LVC652PWDH |
Philips Semiconductors
Product specification
74LVC652
Octal transceiver/register with dual enable (3-State)
2
1998 Jul 29
853-2104 19803
*FEATURES
Wide supply voltage range of 1.2V to 3.6V
In accordance with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
5 Volt tolerant inputs/outputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC652 is a high performance, low-power, low-voltage
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC652 consist of 8 non-inverting bus transceiver circuits
with 3-State outputs, D-type flip-flops and control circuitry arranged
for multiplexed transmission of data directly from the internal
registers. Data on the ‘A’ or ‘B’ or both buses, will be stored in the
internal registers, at the appropriate clock inputs (CPAB or CPBA)
regardless of the select inputs (SAB and SBA) or output enable
(OEAB and OEBA) control inputs. Depending on the select inputs
SAB and SBA data can directly go from input to output (real time
mode) or data can be controlled by the clock (storage mode), this is
when the OEn inputs this operating mode permits. The output
enable inputs OEAB and OEBA determine the operation mode of
the transceiver.
When OEAB is LOW, no data transmission from An to Bn is possible
and when OEBA is HIGH, there is no data transmission from Bn to
An possible. When SAB and SBA are in the real time transfer mode,
it is also possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration each output reinforces its input.
QUICK REFERENCE DATA
GND = 0V; T
amb
= 25
°
C; t
r
= t
f
SYMBOL
2.5 ns
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
Propagation delay
A
n
to B
n
; B
n
to A
n
Maximum clock frequency
Input capacitance
Power dissipation capacitance per latch
C
L
= 50pF
V
CC
= 3.3V
5.0
150
5.0
45
ns
f
max
C
I
C
PD
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W)
P
D
= C
PD
V
CC2
x f
i
Σ
(C
L
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
V
CC2
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
MHz
pF
pF
Notes 1, 2
V
CC2
f
o
) where:
ORDERING AND PACKAGE INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
–40
°
C to +85
°
C
74LVC652 D
74LVC652 D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°
C to +85
°
C
–40
°
C to +85
°
C
74LVC652 DB
74LVC652 DB
SOT340-1
24-Pin Plastic TSSOP Type I
74LVC652 PW
4LVC652PW DH
SOT355-1
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