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參數(shù)資料
| 型號： | 4LVC652PWDH |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal transceiver/register with dual enable 3-State |
| 中文描述： | LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24 |
| 文件頁數(shù)： | 8/14頁 |
| 文件大小： | 147K |
| 代理商： | 4LVC652PWDH |
Philips Semiconductors
Product specification
74LVC652
Octal transceiver/register with dual enable (3-State)
1998 Jul 29
8
AC CHARACTERISTICS
GND = 0 V; t
r
= t
f
2.5 ns; C
L
= 50 pF
LIMITS
V
CC
= 2.7V
MIN
SYMBOL
PARAMETER
WAVEFORM
V
CC
= 3.3V
±
0.3V
MIN
TYP
1
V
CC
= 1.2V
MIN
UNIT
MAX
MAX
TYP
t
PHL
/t
PLH
Propagation delay
An to Bn, Bn to An
Propagation delay
CP
AB
, CP
BA
to B
n
, A
n
Propagation delay
S
AB
, S
BA
to B
n
, A
n
3-State output enable time
OE
AB
to Bn
3-State output disable time
OE
AB
to Bn
3-State output enable time
OE
BA
to An
3-State output disable time
OE
BA
to An
Clock pulse width
HIGH or LOW
CP
AB
or CP
BA
Set-up time
An, Bn to CP
AB
, CP
BA
Hold time
An, Bn to CP
AB
, CP
BA
Maximum clock pulse
frequency
Figures 1, 5
1.5
4.6
7.9
1.5
9.2
1.5
24
ns
t
PHL/
t
PLH
Figures 2, 5
1.5
5.2
8.9
1.5
11
1.5
26
ns
t
PHL/
t
PLH
Figures 3, 5
1.5
5.2
8.8
1.5
11
1.5
27
ns
t
PZH
/t
PZL
Figures 4, 5
1.5
4.8
8.0
1.5
10
1.5
20
ns
t
PHZ
/t
PLZ
Figures 4, 5
1.5
4.4
8.0
1.5
10
1.5
10
ns
t
PZH
/t
PZL
Figures 4, 5
1.5
4.8
8.0
1.5
10
1.5
20
ns
t
PHZ
/t
PLZ
Figures 4, 5
1.5
4.4
8.0
1.5
10
1.5
10
ns
t
W
Figures 4, 5
–
3.0
–
3.0
–
–
–
ns
t
su
Figure 2
1.5
0.5
–
1.5
–
–
–
ns
t
h
Figure 2
1.0
0
–
1.0
–
–
–
ns
f
max
Figure 2
7.5
150
–
–
–
–
–
MHz
NOTE:
1. These typical values are at V
CC
= 3.3V and T
amb
= 25
°
C.
AC WAVEFORMS
V
M
= 1.5V at V
CC
V
M
= 0.5V * V
CC
at V
CC
V
OL
and V
OH
are the typical output voltage drop that occur with the
output load.
V
X
= V
OL
+ 0.3V at V
CC
2.7V
V
X
= V
OL
+ 0.1V
CC
at V
CC
<
2.7V
V
Y
= V
OH
– 0.3V at V
CC
2.7V
V
Y
= V
OH
– 0.1V
CC
at V
CC
<
2.7V
2.7V
2.7V
SV00772
VM
VM
An, Bn
INPUT
Bn, An
OUTPUT
tPHL
tPLH
GND
VOL
VI
VOH
Figure 1. Input An, Bn to output Bn, An propagation delays.
SV00773
VM
An, Bn
INPUT
CPAB, CPBA
OUTPUT
Bn, An
OUTPUT
VM
tW
tPHL
tPLH
1/fmax
tsu
th
tsu
th
GND
VOL
VOL
VI
VOH
VOH
Figure 2. A
n
, B
n
to CP
AB
, CP
BA
set-up and hold times, clock
CP
AB
, CP
BA
pulse width, maximum clock pulse frequency and
the CP
AB
, CP
BA
to output B
n
, A
n
propagation delays.
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