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參數(shù)資料
| 型號： | 5102ALPRP |
| 廠商： | MAXWELL TECHNOLOGIES |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, DFP44 |
| 封裝： | LDFP-44 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 140K |
| 代理商： | 5102ALPRP |
M
em
or
y
5
0627.00Rev2
All data sheets are subject to change without notice
2000 Space Electronics Inc.
All rights reserved.
16-BIT, 20 KHZ A/D CONVERTER
5102ALPRP
HOLD to SSH Falling 6
t
dfsh2
--
60
--
ns
HOLD to TRK1, TRK2, Falling 6
t
dfsh1
66t
clk
--
68t
clk + 260
ns
HOLD to TRK1, TRK2, SSH Rising 6
t
drsh
--
120
--
ns
HOLD Pulse Width 7
t
hold
1t
clk + 20
--
63t
clk
ns
HOLD to CH1/2 Edge 6
t
dhlri
300
--
64t
clk
ns
HOLD Falling to CLKIN Falling 7
t
hcf
275
--
1t
clk + 10
ns
PDT and RBT Modes
SCLK Input Pulse Period
t
sclk
500 8
--
ns
SCLK Input Pulse Width Low
t
sckll
200 8
--
ns
SCLK Input Pulse Width High
t
sclkh
200 8
--
ns
SCLK Input Falling to SDATA Valid
t
dss
--
100
150
ns
HOLD Falling to SDATA Valid - PDT Mode
t
dhs
--
140
230
ns
TRK1, TRK2 Falling to SDATA Valid 9
t
dts
--
65
125
ns
FRN and SSC Modes
SCLK Output Pulse Width Low
t
slkl
--
2t
clk
--
t
clk
SCLK Output Pulse Width High
t
slkh
--
2t
clk
--
t
clk
SDATA Valid Before Rising SCLK
t
ss
2t
clk - 100
--
ns
SDATA Valid After Rising SCLK
t
sh
2t
clk - 100
--
ns
SDL Falling to 1st Rising SCLK
t
rsclk
--
2t
clk
--
ns
Last Rising SCLK to SDL Rising
t
rsdl
--
2tclk
2t
clk + 200
ns
HOLD Falling to 1st Falling SCLK
t
hfs
6t
clk
--
8t
clk + 200
ns
CH1/2 Edge to 1st Falling SCLK
t
chfs
--
7t
clk
--
t
clk
1. Minimum CLKIN period is 0.625 s is FRN mode (20 kHz sample rate).
2. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency is 1.6 MHz in FRN mode (20 kHz sample rate).
3. With a 2.0 MHz crystal, two 33 pF loading capacitors and a 10 M
parallel resistor.
4. Guaranteed by initial characterization (5102A die).
5. These times are for FRN mode.
6. These times are for PDT and RBT modes.
7. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must be latched by a falling edge of CLKIN. Conversion will begin on
the next rising edge of CLKIN after HOLD is latched.
8. Sample tested at 25 oC. Go - No Go.
9. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid t
dss time after the next falling SCLK.
TABLE 4. 5102ALPRP SWITCHING CHARACTERISTICS
(T
A = TMIN
TO
T
MAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; I
NPUTS
: LOGIC 0 = 0V, LOGIC 1 = VD+; C
L = 50
P
F)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
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