參數(shù)資料
型號: 5102ALPRP
廠商: MAXWELL TECHNOLOGIES
元件分類: ADC
英文描述: 2-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, DFP44
封裝: LDFP-44
文件頁數(shù): 9/12頁
文件大?。?/td> 140K
代理商: 5102ALPRP
M
em
or
y
6
0627.00Rev2
All data sheets are subject to change without notice
2000 Space Electronics Inc.
All rights reserved.
16-BIT, 20 KHZ A/D CONVERTER
5102ALPRP
LPT OPERATION
Latchup Protection Technology (LPT) automatically detects an increase in the supply current of the 5102APLPT converter due to a single event effect
and internally cycle the power to the converter off, then on, which restores the steady state operation of the device.
If data outputs are connected to a bus with other bus driver circuits, all external data bus drivers must be tri-stated and individual pull up resistors to the
supply voltage (if used on the data bus) must no be less than 10 K
typical to assure proper single event effect recovery.
STATUS can also be used to generate an input to the system data processor indicating that an LPT cycle has occurred, and the protected device output
accuracy may not be met until after the respective recovery time to the event. The STATUS signal is generated from an advanced CMOS logic gate output.
This output may not exhibit a monotonic fall time and may even oscillate briefly while power is being restored to the protected device and the decoupling
capacitance is charged. Loading on the STATUS output should be minimized because this signal is used internally by the 5102ALPRP . It is recommended
that load current not exceed 2 mA and load capacitance be kept will below 1000 pF.
TABLE 5. 5102ALPRP DIGITAL CHARACTERISTICS
(T
A = TMIN
TO
T
MAX; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Calibration Memory Retention Power Supply Voltage VA+ & VD+ 1
1. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be allowed to go positive. AIN1, AIN2 or V
REF must not be greater
than VA+ or VD+. This parameter is guaranteed by characterization.
V
MR
2.0
--
V
High-Level Input Voltage
V
IH
2.0
--
V
Low-Level Input Voltage
V
IL
--
0.8
V
High-Level Output Voltage 2
2. I
OUT = -100 A. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40 A.
V
OH
(VD+) -1.0
--
V
Low-Level Output Voltage - I
OUT = 1.6 mA
V
OL
--
0.4
V
Input Leakage Current
I
IN
--
10
A
Digital Output Pin Capacitance
C
OUT
--
9
--
pF
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