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參數(shù)資料
| 型號： | 550CE128M500DG |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 128.5 MHz, CMOS OUTPUT |
| 封裝： | ROHS COMPLIANT PACKAGE-6 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 230K |
| 代理商： | 550CE128M500DG |
Si550
6
Rev. 0.6
Table 7. CLK± Output Phase Noise (Typical)
Offset Frequency
74.25 MHz
90 ppm/V
LVPECL
491.52 MHz
45 ppm/V
LVPECL
622.08 MHz
135 ppm/V
LVPECL
Units
100 Hz
1kHz
10 kHz
100 kHz
1MHz
10 MHz
100 MHz
–87
–114
–132
–142
–148
–150
n/a
–75
–100
–116
–124
–135
–146
–147
–65
–90
–109
–121
–134
–146
–147
dBc/Hz
Table 8. Absolute Maximum Ratings1
Parameter
Symbol
Rating
Units
Maximum Operating Temperature
TAMAX
85
C
Supply Voltage
VDD
–0.5 to +3.8
Volts
Input Voltage
VI
–0.5 to VDD + 0.3
Volts
Storage Temperature
TS
–55 to +125
C
ESD Sensitivity (HBM, per JESD22-A114)
ESD
2500
Volts
Soldering Temperature (Pb-free profile)2
TPEAK
260
C
Soldering Temperature Time @ TPEAK (Pb-free profile)2
tP
20–40
seconds
Notes:
1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional
operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for
extended periods may affect device reliability.
2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download from
www.silabs.com/VCXO for further information, including soldering profiles.
Table 9. Environmental Compliance
The Si550 meets the following qualification test requirements.
Parameter
Conditions/Test Method
Mechanical Shock
MIL-STD-883F, Method 2002.3 B
Mechanical Vibration
MIL-STD-883F, Method 2007.3 A
Solderability
MIL-STD-883F, Method 203.8
Gross & Fine Leak
MIL-STD-883F, Method 1014.7
Resistance to Solvents
MIL-STD-883F, Method 2016
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