參數(shù)資料
型號: 5962-0050401QXC
廠商: E2V TECHNOLOGIES PLC
元件分類: ADC
英文描述: 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QFP68
封裝: QFP-68
文件頁數(shù): 43/57頁
文件大小: 1276K
代理商: 5962-0050401QXC
Rev.2.10
Oct 25, 2006
Page 48 of 326
REJ03B0152-0210
M306H7MG-XXXFP/MC-XXXFP/FGFP
6. INTERRUPTS
6.5
Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order
they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the FLG register’s I flag, IPL, and each interrupt control register’s ILVL2 to ILVL0 bits to enable/disable the
maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each interrupt control register.
Figure 6.3 shows the interrupt control registers.
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