參數(shù)資料
型號(hào): 5962-8766001GA
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): MOSFETs
英文描述: 2 CHANNEL, BUF OR INV BASED MOSFET DRIVER, MBCY8
封裝: METAL CAN-8
文件頁(yè)數(shù): 12/15頁(yè)
文件大?。?/td> 784K
代理商: 5962-8766001GA
MAX706P/R/S/T
,MAX706AP/AR/AS/A
T
,MAX708R/S/T
+3V Voltage Monitoring, Low-Cost P
Supervisory Circuits
6
_______________________________________________________________________________________
Pin Description
MAX706P
MAX706AP
MAX706R/S/T,
MAX706AR/AS/AT
MAX708R/S/T
SO/DIP
MAX
SO/DIP
MAX
SO/DIP MAX
NAME
FUNCTION
13
1
3
1
3
MR
Active-Low, Manual-Reset Input. Pull MR below 0.6V to trigger a
reset pulse. MR is TTL/CMOS compatible when VCC = 5V and can
be shorted to GND with a switch. MR is internally connected to a
70A source current. Connect to VCC or leave unconnected.
24
2
4
2
4
VCC
Supply Voltage Input
3
5
3
5
3
5
GND
Ground
4
6
4
6
4
6
PFI
Adjustable Power-Fail Comparator Input. Connect PFI to a
resistive divider to set the desired PFI threshold. When PFI is
less than 1.25V, PFO goes low and sinks current; otherwise,
PFO remains high. Connect PFI to GND if not used.
57
5
7
5
7
PFO
Active-Low, Power-Fail Comparator Output. PFO asserts when
PFI is below the internal 1.25V threshold. PFO deasserts when
PFI is above the internal 1.25V threshold. Leave PFO
unconnected if not used.
6
8
6
8
WDI
Watchdog Input. A falling or rising transition must occur at
WDI within 1.6s to prevent WDO from asserting (see Figure 4).
The internal watchdog timer is reset to zero when reset is
asserted or when transition occurs at WDI. The watchdog
function for the MAX706P/R/S/T can not be disabled. The
watchdog timer for the MAX706AP/AR/AS/AT disables when
WDI input is left open or connected to a tri-state output in its
high-impedance state with a leakage current of less than
600nA.
7
1
8
2
RESET
Active-High Reset Output. RESET remains high when VCC is
below the reset threshold or MR is held low. It remains low for
200ms after the reset conditions end (Figure 3).
82
8
2
WDO
Active-Low Watchdog Output. WDO goes low when a
transition does not occur at WDI within 1.6s and remains low
until a transition occurs at WDI (indicating the watchdog
interrupt has been serviced). WDO also goes low when VCC
falls below the reset threshold; however, unlike the reset
output signal, WDO goes high as soon as VCC rises above
the reset threshold.
——
7
1
7
1
RESET
Active-Low Reset Output. RESET remains low when VCC is
below the reset threshold or MR is held low. It remains low for
200ms after the reset conditions end (Figure 3).
6
8
N.C.
No Connection. Not internally connected.
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