- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68795 > 5962-8962902LX (ANALOG DEVICES INC) SPECIALTY ANALOG CIRCUIT, CDIP24 PDF資料下載
參數(shù)資料
| 型號： | 5962-8962902LX |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, CDIP24 |
| 封裝： | CERDIP-24 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大小： | 485K |
| 代理商： | 5962-8962902LX |
–10–
REV. B
AD7569/AD7669
INTERNAL CLOCK
Clock pulses are generated by the action of an internal current
source charging the external capacitor (CCLK) and this external
capacitor discharging through the external resistor (RCLK).
When a conversion is complete, this internal clock stops operat-
ing and the CLK pin goes to the DGND potential. Connections
for RCLK and CCLK are shown in the operating diagram of Fig-
ure 21. The nominal conversion time versus temperature for the
recommended RCLK and CCLK combination is shown in Figure
6. The internal clock provides a convenient clock source for the
AD7569/AD7669. Due to process variations, the actual operat-
ing frequency for this RCLK/CCLK combination can vary from
device to device by up to
±25%.
Figure 6. Conversion Time vs. Temperature for Internal
Clock Operation
DIGITAL INTERFACE
DAC Timing and Control—AD7569
Table II shows the truth table for DAC operation for the
AD7569. The part contains an 8-bit DAC register, which is
loaded from the data bus under control of CS and WR. The
data contained in the DAC register determines the analog out-
put from the DAC. The WR input is an edge-triggered input,
and data is transferred into the DAC register on the rising edge
of WR. Holding CS and WR low does not make the DAC regis-
ter transparent.
Table II. AD7569 DAC Truth Table
CS
WR
RESET
DAC Function
H
DAC Register Unaffected
L
H
DAC Register Unaffected
L
g
H
DAC Register Updated
g
L
H
DAC Register Updated
X
L
DAC Register Loaded with All Zeros
L = Low State, H = High State, X = Don’t Care
The contents of the DAC register are reset to all 0s by an active
low pulse on the RESET line, and for the unipolar output ranges,
the output remains at 0 V after RESET returns high. For the bi-
polar output ranges, a low pulse on RESET causes the output to
go to negative full scale. In unipolar applications, the RESET line
can be used to ensure power-up to 0 V on the AD7569 DAC out-
put and is also useful when used as a zero override in system cali-
bration cycles. If the RESET input is connected to the system
At the end of conversion, the SAR contents are transferred to
the output latch, and the SAR is reset in readiness for a new
conversion. A single conversion lasts for 8 input clock cycles.
Figure 4. Operating Waveforms Using External Clock
ANALOG INPUT
The analog input of the AD7569/AD7669 feeds into an on-chip
track-and-hold amplifier. To accommodate different full-scale
ranges, the analog input signal is conditioned by a gain/offset
network that conditions all input ranges so the internal ADC al-
ways works with a 0 V to +1.25 V signal. As a result, the input
current on the VIN input varies with the input range selected as
shown in Figure 5.
Figure 5. Equivalent VIN Circuit
TRACK-AND-HOLD
The track-and-hold (T/H) amplifier on the analog input of the
AD7569/AD7669 allows the ADC to accurately convert an in-
put sine wave of 2.5 V peak-to-peak amplitude up to a fre-
quency of 200 kHz, the Nyquist frequency of the ADC when
operated at its maximum throughput rate of 400 kHz. This
maximum rate of conversion includes conversion time and time
between conversions. Because the input bandwidth of the T/H
amplifier is much larger than 200 kHz, the input signal should
be band-limited to avoid converting high-frequency noise
components.
The operation of this T/H amplifier is essentially transparent to
the user. The T/H amplifier goes from its tracking mode to its
hold mode at the start of conversion. This occurs when the
ADC receives a conversion start command from either ST or
CS
& RD. At the end of conversion (BUSY going high), the
T/H reverts back to tracking the input signal.
EXTERNAL CLOCK
The AD7569/AD7669 ADC can be used with its on-chip clock
or with an externally applied clock. When using an external
clock, the CLK input of the AD7569/AD7669 may be driven
directly from 74HC, 4000B series buffers (such as 4049) or
from TTL buffers. When conversion is complete, the internal
clock is disabled. The external clock can continue to run be-
tween conversions without being disabled. The mark/space ratio
of the external clock can vary from 70/30 to 30/70.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962-8963401CA | QUAD OP-AMP, 2500 uV OFFSET-MAX, 34 MHz BAND WIDTH, CDIP14 |
| 5962-8963401CX | QUAD OP-AMP, 2500 uV OFFSET-MAX, 34 MHz BAND WIDTH, CDIP14 |
| 5962-89635012X | OP-AMP, 3000 uV OFFSET-MAX, 10 MHz BAND WIDTH, CQCC20 |
| 5962-8963501PX | OP-AMP, 3000 uV OFFSET-MAX, 10 MHz BAND WIDTH, CDIP8 |
| 5962-8964301XC | OP-AMP, 10000 uV OFFSET-MAX, 40 MHz BAND WIDTH, MBCY12 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 5962-8963001EA | 制造商:National Semiconductor Corporation 功能描述:Dual Receiver RS-232/RS-422/RS-423 16-Pin CDIP Rail 制造商:National Semiconductor 功能描述:Dual Receiver RS-232/RS-422/RS-423 16-Pin CDIP Rail |
| 5962-8963101PA | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| 5962-8963201PA | 制造商:Rochester Electronics LLC 功能描述:SMD HA7-5112 DUAL LOW NOISE OP AMP 8 LD CDIP - Bulk |
| 5962-89635012A | 制造商:Intersil Corporation 功能描述:OP AMP SGL GP 15V 20CLCC - Rail/Tube |
| 5962-8963501PA | 制造商:Intersil Corporation 功能描述:SMD VERSIO HA7-5101/883 NOT DUAL MARKED - Rail/Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。