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參數資料
| 型號： | 5962-8967402QX |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數： | 29/50頁 |
| 文件大?。?/td> | 520K |
| 代理商： | 5962-8967402QX |
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PIN DESCRIPTIONS
Power Supply Connections
VD+ – Positive Digital Power, PIN 11.
Positive digital power supply. Nominally +5 volts.
VD- – Negative Digital Power, PIN 36.
Negative digital power supply. Nominally -5 volts.
DGND – Digital Ground, PIN 10.
Digital ground.
VA+ – Positive Analog Power, PIN 25.
Positive analog power supply. Nominally +5 volts.
VA- – Negative Analog Power, PIN 30.
Negative analog power supply. Nominally -5 volts.
AGND – Analog Ground, PIN 27.
Analog ground.
Oscillator
CLKIN – Clock Input, PIN 20.
All conversions and calibrations are timed from a master clock which can either be supplied by
driving this pin with an external clock signal, or can be internally generated by tying this pin to
DGND.
Digital Inputs
HOLD – Hold, PIN 1.
A falling transition on this pin sets the CS5012A/14/16 to the hold state and initiates a conversion.
This input must remain low at least one CLKIN cycle plus 50 ns.
CS – Chip Select, PIN 21.
When high, the data bus outputs are held in a high impedance state and the input to CAL and
INTRLV are ignored. A falling transition initiates or terminates burst or interleave calibration
(depending on the status of CAL and INTRLV) and a rising transition latches both the CAL and
INTRLV inputs. If RD is low, the data bus is driven as indicated by BW and A0.
RD – Read, PIN 22.
When RD and CS are both low, data is driven onto the data bus. If either signal is high, the data
bus outputs are held in a high impedance state. The data driven onto the bus is determined by BW
and A0.
CS5012A, CS5014, CS5016
DS14F6
35
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