參數(shù)資料
型號(hào)： 5962-8967402QX
廠商： CIRRUS LOGIC INC
元件分類(lèi)： ADC
英文描述： 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
封裝： CERAMIC, DIP-40
文件頁(yè)數(shù)： 3/50頁(yè)
文件大?。?/td> 520K
代理商： 5962-8967402QX
THEORY OF OPERATION
The CS5012A/14/16 family utilize a successive
approximation conversion technique. The analog
input is successively compared to the output of a
D/A converter controlled by the conversion algo-
rithm. Successive approximation begins by
comparing the analog input to the DAC output
which is set to half-scale (MSB on, all other bits
off). If the input is found to be below half-scale,
the MSB is reset to zero and the input is com-
pared to one-quarter scale (next MSB on, all
others off). If the input were above half-scale, the
MSB would remain high and the next compari-
son would be at three-quarters of full scale. This
procedure continues until all bits have been exer-
cised.
A unique charge redistribution architecture is
used to implement the successive approximation
algorithm. Instead of the traditional resistor net-
work, the DAC is an array of binary-weighted
capacitors. All capacitors in the array share a
common node at the comparator’s input. Their
other terminals are capable of being connected to
AIN, AGND, or VREF (Figure 1). When the de-
v ice is not calibrating or converting, all
capacitors are tied to AIN forming Ctot. Switch
S1 is closed and the charge on the array, Qin,
tracks the input signal Vin (Figure 2a).
When the conversion command is issued, switch
S1 opens as shown in Figure 2b. This traps
charge Qin on the comparator side of the capaci-
tor array and creates a floating node at the
comparator’s input. The conversion algorithm op-
erates on this fixed charge, and the signal at the
analog input pin is ignored. In effect, the entire
DAC capacitor array serves as analog memory
AIN
VREF
AGND
CC/2
C/4
C/8
MSB
LSB
Bit 11
Bit 10
Bit 9
Bit 8
Bit 0
Dummy
C/X
S1
Bit 13
Bit 15
Bit 12
Bit 14
Bit 11
Bit 13
Bit 10
Bit 12
CS5012A:
CS5014:
CS5016:
C/X
X = 2048
X = 8192
X = 32768
CS5012A
CS5014
CS5016
C
= C + C/2 + C/4 + ... + C/X
tot
Figure 1. Charge Redistribution DAC
(1-D)C tot
in
Q
+
-
Vfn
To MCU
S1
Ctot
D .
VREF
AGND
D
for
VREF
Vin
=0V
fn
V
=
Figure 2b. Convert Mode
in
Q
Ctot
S1
Vin
AIN
+
-
To MCU
= Vin Ctot
in
-Q
Figure 2a. Tracking Mode
CS5012A, CS5014, CS5016
DS14F6
11
相關(guān)PDF資料
PDF描述
5962-8967901XX 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967402XX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967401QX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967401XX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967901QX 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
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