參數(shù)資料
型號(hào)： 5962-8967601QX
廠商： CIRRUS LOGIC INC
元件分類： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
封裝： CERAMIC, DIP-40
文件頁數(shù)： 27/50頁
文件大小： 520K
代理商： 5962-8967601QX
Figure 36. CS5012A/14/16 System Connection Diagram
26
28
29
30
25
27
11
10
36
VREF
AIN
REFBUF
VA-
AGND
VA+
VD+
DGND
VD-
+5V
-5V
10
10
Voltage
Reference
Reset
Generator
Data
Processor
Serial
Data
Interface
(optional)
Clock
Source
(optional)
Control
Logic
Mode
Select *
Analog
Supply
Source
Signal
Analog
Supply
Analog
TST
BW
RESET
A0
CAL
D0-D15
SCLK
SDATA
CLKIN
24
33
20
40
39
8 or 16
38
37
1
35
34
21
22
23
32
31
0.1
F
0.01
F
0.1
F
0.1
F
May be
microprocessor
or discrete logic.
0.1
F
INTRLV
EOC
EOT
HOLD
BP/UP
RD
CS
0.1
F
CS5012A
or
VREF
±VREF
0
10
F
Signal
Conditioning
1000 pF
200
CS5014
CS5016
Unused Logic inputs should only
be connected to VD+ or DGND.
* BWand BP/UP should always
be terminated to VD+ or DGND,
For best dynamic
S/(N+D) performance.
or driven by a logic gate.
Function
RST
A0
CAL
Hold and Start Convert
Initiate Burst Calibration
Stop Burst Cal and Begin Track
Initiate Interleave Calibration
Terminate Interleave Cal
Read Output Data
Read Status Register
High Impedance Data Bus
Reset
0
X
1
X
*
1
0
*
X
0
X
0
X
1
X
0
1
X
1
0
X
0
1
X
0
X
1
X
1
X
0
HOLD
CS
INTRLV
RD
Table 4. CS5012A/14/16 Truth Table
*
The status of A0 is not critical to the operation specified. However, A0 should not be low with
CS and HOLD low, or a software reset will result.
CS5012A, CS5014, CS5016
DS14F6
33
相關(guān)PDF資料
PDF描述
5962-8967601XX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967602QX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967602XX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967402QX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967901XX 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
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