參數(shù)資料
型號(hào)： 5962-8967601XX
廠商： CIRRUS LOGIC INC
元件分類(lèi)： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
封裝： CERAMIC, LCC-44
文件頁(yè)數(shù)： 13/50頁(yè)
文件大?。?/td> 520K
代理商： 5962-8967601XX
Peaking in the reference’s output impedance can
occur because of capacitive loading at its output.
Any peaking that might occur can be reduced by
placing a small resistor in series with the capaci-
tors (Figure 10). The equation in Figure 10 can
be used to help calculate the optimum value of R
for a particular reference. The term "fpeak" is the
frequency of the peak in the output impedance of
the reference before the resistor is added.
The CS5012A/14/16 can operate with a wide
range of reference voltages, but signal-to-noise
performance is maximized by using as wide a
signal range as possible. The recommended refer-
ence voltage is between 2.5 and 4.5 V for the
CS5012A and 4.5 V for the CS5014/16. The
CS5012A/14/16 can actually accept reference
voltages up to the positive analog supply. How-
ever, the buffer’s offset may increase as the
reference voltage approaches VA+ thereby in-
creasing external drive requirements at VREF. A
4.5V reference is the maximum reference voltage
recommended. This allows 0.5V headroom for
the internal reference buffer. Also, the buffer en-
lists the aid of an external 0.1
F ceramic
capacitor which must be tied between its output,
REFBUF, and the negative analog supply, VA-. For
more information on references, consult the applica-
tion note: Voltage References for the CS501X Se-
ries of A/D Converters. For an example of using
the CS5012A/14/16 with a 5 volt reference, see
the application note: A Collection of Application
Hints for the CS501X Series of A/D Converters.
Analog Input Connection
The analog input terminal functions similarly to
the VREF input after each conversion when
switching into the track mode. During the first
six CLKIN cycles in the track mode, the buffered
version of the analog input is used for pre-charg-
ing the capacitor array. An additional period is
required for fine-charging directly from AIN to
VREF
REFBUF
VA-
0.1
F
-5V
R
29
28
30
ref
V
C1
1.0
F
0.01
F
C2
+Vee
CS5012A
CS5014
CS5016
1
R=
2
π (C1 + C2) fpeak
Figure 10. Reference Connections
In
te
rn
a
lC
h
a
rg
e
E
rr
o
r(L
S
B
’s
)
Fine-Charge
Pre-Charge
Acquisition Time (us)
0.5
1.0
1.5
2.0
2.5
(Delay from EOC)
+12.5
0
-12.5
-25.0
+50
0
-50
-100
+200
0
-200
-400
CS5012A
CS5014
CS5016
Figure 11. Internal Acquisition Time
CS5012A, CS5014, CS5016
20
DS14F6
相關(guān)PDF資料
PDF描述
5962-8967602QX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967602XX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967402QX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967901XX 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967402XX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
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