參數(shù)資料
型號(hào)： 5962-8967602QX
廠商： CIRRUS LOGIC INC
元件分類： ADC
英文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
封裝： CERAMIC, DIP-40
文件頁(yè)數(shù)： 30/50頁(yè)
文件大小： 520K
代理商： 5962-8967602QX
A0 – Read Address, PIN 23.
Determines whether data or status information is placed onto the data bus. When high during the
read operation, converted data is placed onto the data bus; when low, the status register is driven
onto the bus.
BP/UP – Bipolar/Unipolar Input Select, PIN 24.
When high, the device is configured with a bipolar transfer function ranging from -VREF to
+VREF. Encoding is in an offset binary format, with the mid-scale code 100...0000 centered at
AGND. When low, the device is configured for a unipolar transfer function from AGND to
VREF. Unipolar encoding is in straight binary format. Once calibration has been performed, either
bipolar or unipolar mode may be selected without the need to recalibrate.
RST – Reset, PIN 32.
When taken high for at least 100 ns, all internal digital logic is reset. Upon being taken low, a full
calibration sequence is initiated.
BW – Bus Width Select, PIN 33.
When hard-wired high, all 12 data bits are driven onto the bus simultaneously during a data read
cycle. When low, the bus is in a byte wide format. On the first read following a conversion, the
eight MSB’s are driven onto D0-D7. A second read cycle places the four LSB’s with four trailing
zeros on D0-D7. Subsequent reads will toggle the higher/lower order byte. Regardless of BW’s
status, a read cycle with A0 low yields the status information on D0-D7.
INTRLV – Interleave, PIN 34.
When latched low using CS, the device goes into interleave calibration mode. A full calibration
will complete every 2,014 conversions in the CS5012A, and every 72,051 conversions in the
CS5014/16. The effective conversion time extends by 20 clock cycles.
CAL – Calibrate, PIN 35. (See Addendum appending this data sheet))
When latched high using CS, burst calibration results. The device cannot perform conversions
during the calibration period which will terminate only once CAL is latched low again.
Calibration picks up where the previous calibration left off, and calibration cycles complete every
58,280 CLKIN cycles in the CS5012A, and every 1,441,020 CLKIN cycles in the CS5014/16 . If
the device is converting when a calibration is signaled, it will wait until that conversion completes
before beginning.
Analog Inputs
AIN – Analog Input, PIN 26.
Input range in the unipolar mode is zero volts to VREF. Input range in bipolar mode is -VREF to
+VREF. The output impedance of buffer driving this input should be less than or equal to 200
.
CS5012A, CS5014, CS5016
36
DS14F6
相關(guān)PDF資料
PDF描述
5962-8967602XX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967402QX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967901XX 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967402XX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967401QX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
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