參數(shù)資料
型號: 5962-8967901XX
廠商: CIRRUS LOGIC INC
元件分類: ADC
英文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
封裝: CERAMIC, LCC-44
文件頁數(shù): 23/50頁
文件大小: 520K
代理商: 5962-8967901XX
CS5012A ANALOG CHARACTERISTICS (continued)
CS5012A-K
CS5012A-B
CS5012-T
Parameter*
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
Specified Temperature Range
0 to +70
-40 to +85
-55 to +125
°C
Analog Input
Aperture Time
25
ns
Aperture Jitter
100
ps
Input Capacitance
(Note 4)
Unipolar Mode CS5012
CS5012A
Bipolar Mode
CS5012
CS5012A
275
103
165
72
375
137
220
96
275
103
165
72
375
137
220
96
275
103
165
72
375
137
220
96
pF
Conversion & Throughput
Conversion Time
-7
(Notes 5 and 6)
-12
7.2
12.25
7.2
12.25
s
Acquisition Time
-7
(Note 6)
-12
2.5
3.0
2.8
3.75
2.5
3.0
2.8
3.75
3.0
3.75
s
Throughput
-7
(Note 6)
-12
100
62.5
100
62.5
kHz
Power Supplies
DC Power Supply Currents
(Note 7)
IA+
IA-
(CS5012)
ID+
(CS5012A)
ID+
ID-
12
-12
3
6
-3
19
-19
6
7.5
-6
12
-12
3
6
-3
19
-19
6
7.5
-6
12
-12
3
-3
19
-19
6
-6
mA
Power Dissipation
(Note 7)
150
250
150
250
150
250
mW
Power Supply Rejection
(Note 8)
Positive Supplies
Negative Supplies
84
dB
Notes:
4. Applies only in track mode. When converting or calibrating, input capacitance will not exceed 15 pF.
5. Measured from falling transition on HOLD to falling transition on EOC.
6. Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions.
The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s
conversion clock, interleave calibrate is disabled, and operation is from the full-rated, external clock.
Refer to the section
Conversion Time/Throughput for a detailed discussion of conversion timing.
7. All outputs unloaded. All inputs CMOS levels.
8. With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply
rejection versus frequency.
CS5012A
DS14F6
3
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