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| 型號(hào)： | 5962-8990502EA |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.2 A SWITCHING CONTROLLER, 1150 kHz SWITCHING FREQ-MAX, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁(yè)數(shù)： | 17/18頁(yè) |
| 文件大?。?/td> | 477K |
| 代理商： | 5962-8990502EA |
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UC1823A,UC2823A, UC2823B,
UC3823A,UC3823B,UC1825A,
UC2825A,UC2825B,UC3825A,UC3825B
SLUS334D AUGUST 1995 REVISED NOVEMBER 2008
www.ti.com
8
UVLO, SOFT-START AND FAULT MANAGEMENT
Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier
output is also forced low. While the internal 9-
A source charges the SS pin, the error amplifier output follows until closed
loop regulation takes over.
Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is then discharged
by a 250-
A current sink. No more output pulses are allowed until soft-start is fully discharged and ILIM is below 1.2 V. At
this point the fault latch resets and the chip executes a soft-start.
Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor does not
discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions.
UDG95106
Figure 5. Soft-Start and Fault Waveforms
ACTIVE LOW OUTPUTS DURING UVLO
The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate.
Figure 6. Output Voltage vs Output Current
UDG95108
UDG95106
Figure 7. Output V and I During UVLO
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