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參數(shù)資料
| 型號(hào)： | 5962-8997301PX |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | OP-AMP, 6000 uV OFFSET-MAX, 179 MHz BAND WIDTH, CDIP8 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 314K |
| 代理商： | 5962-8997301PX |
Application Division
Understanding the Loop Gain
Referring to the equivalent circuit of
Figure 3, any current
flowing in the inverting input is amplified to a voltage at the
output through the transimpedance gain shown on the plots
on page 3. This Z(s) is analogous to the open-loop gain of a
voltage feedback amplifier.
Developing the non-inverting frequency response for the
topology of
Figure 3 yields:
Equation 1
where LG is the loop gain defined by,
Equation 2
Equation 1 has a form identical to that for a voltage feedback
amplifier with the differences occurring in the LG expression.
For an idealized treatment, set Z
i=0 which results in a very
simple LG = Z(s)/R
f(Derivation of the transfer function for the
case where Z
i = 0 is given in Application Note AN300-1).
Using the Z(s) (open-loop transimpedance gain) plot shown
on the previous page and dividing by the recommended R
f =
1.5k
, yields a large loop gain at DC. As a result, Equation
1 shows that the closed-loop gain at DC is very close to
(1+R
f/Rg).
At higher frequencies, the roll-off of Z(s) determines the
closed-loop frequency response which, ideally, is dependent
only on R
f. The specifications reported on the previous
pages are therefore valid only for the specified R =
1.5k
. Increasing R from 1.5k will decrease the loop gain
and band width, while decreasing it will increase the loop
gain possibly leading to inadequate phase margin and
closed-loop peaking. Conversely, fixing R
f will hold the fre-
quency response constant while the closed-loop gain can be
adjusted using R
g.
The CLC401 departs from this idealized analysis to the
extent that the inverting input impedance is finite. With the
low quiescent power of the CLC401, Z = 50
leading to drop
in loop gain and bandwidth at high gain settlings, as given by
Equation 2. The second term is Equation 2 accounts for the
division in feedback current that occurs between Z
i and
R
f\Rg at the inverting node of the CLC400. This decrease in
bandwidth can be circumvented as described in “Increasing
Bandwidth at High Gains.”
DC Accuracy and Noise
Since the two inputs for the CLC401 are quite dissimilar, the
noise and offset error performance differs somewhat from
that of a standard differential input amplifier. Specifically, the
inverting input current noise is much larger than the
non-inverting current noise. Also the two input bias currents
are physically unrelated rendering bias current cancellation
through matching of the inverting and non-inverting pin re-
sistors ineffective.
In Equation 3, the output offset is the algebraic sum of the
equivalent input voltage and current sources that influence
DC operation. Output noise is determined similarly except
that a root-sum-of-squares replaces the algebraic sum. R
s is
the non-inverting pin resistance.
Equation 3
Output Offset V
O = ±IBNxRS (1+ Rf/Rg) ±
VIO (1+ R
f/Rg) ±IBIxRf
An important observation is that for fixed R
f, offsets as
referred to the input improve as the gain is increased (divide
all terms by 1+R
f/Rg). A similar result is obtained for noise
where noise figure improves as gain increases.
Selecting Between the CLC400 or CLC401
DS012744-15
FIGURE 1. Recommended Non-Inverting Gain Circuit
DS012744-16
FIGURE 2. Recommended Inverting Gain Circuit
DS012744-22
FIGURE 3. Current feedback topology
CLC401
www.national.com
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