Application Division (Continued)
The CLC400 is intended for gains of ±1to±8 while the
CLC401 is designed for gains of ±7to±50. Optimum perfor-
mance is achieved with a feedback resistor of 250
with the
CLC400 and 1.5
with the CLC401- this distinction may be
important in transimpedance applications such as D/A buff-
ering. Although the CLC400 can be used at higher gains, the
CLC401 will provide a wider bandwidth because loop gain
losses due to finite Z
i are lower with the larger CLC401
feedback resistor as explained above. On the other hand,
the lower recommended feedback resistance of the CLC400
minimizes the output errors due to inverting input noise and
bias currents.
Increasing Bandwidth At High Gains
Bandwidth may be increased at high closed-loop gains by
adjusting R
f and Rgto make up for the losses in loop gain that
occur at these high gain settlings due to current division at
the inverting input. An approximate relationship my be ob-
tained by holding the LG expression constant as the gain is
changed from the design point used in the specifications
(that is, R
f = 1.5k and Rg =79). For the CLC401 this
gives,
Equation 4
where A
Vis the desired non-inverting gain. Note that with AV
= +20 we get the specified R
f = 1.5k, while at higher gains,
a lower value gives stable performance with improved band-
width.
Capacitive Feedback
Capacitive feedback should not be used with the CLC401
because of the potential for loop instability. See Application
Note OA-7 for active filter realizations with the CLC401.
Printed Circuit Layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. In the non-inverting configura-
tion, the amplifier is sensitive to stray capacitance to ground
at the inverting input. Hence, the inverting node connections
should be small with minimal coupling to the ground plane.
Shunt capacitance across the feedback resistor should not
be used to compensate for this effect.
Parasitic or load capacitance directly on the output will intro-
duce additional phase shift in the loop degrading the loop
phase margin and leading to frequency response peaking. A
small series resistor before the capacitance effectively de-
couples this effect. The graphs on the preceding page illus-
trate the required resistor value and resulting performance
vs. capacitance.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products) with low parasitic reactances were used
to develop the data sheet specifications. Precision carbon
composition resistors will also yield excellent results. Stan-
dard spirally-trimmed RN55D metal film resistors will work
with the slight decrease in bandwidth due to their reactive
nature at high frequencies.
Evaluation PC boards (part no. CLC730013 for through-hole
and CLC730027 for SOIC) for the CLC401 are available.
CLC401
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