參數(shù)資料
型號(hào)： 5962-9064202QRA
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： ADC
英文描述： 11-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20
封裝： CERAMIC, DIP-20
文件頁(yè)數(shù)： 31/32頁(yè)
文件大?。?/td> 770K
代理商： 5962-9064202QRA
www.ti.com
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
SLAS052G – MARCH 1992 – REVISED JANUARY 2006
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VCC, see (2)
Supply voltage range
-0.5 V to 6.5 V
VI
Input voltage range
-0.3 V to VCC + 0.3 V
VO
Output voltage range
-0.3 V to VCC + 0.3 V
Vref+
Positive reference voltage
VCC + 0.1 V
Vref-
Negative reference voltage
-0.1 V
Peak input current (any input)
±20 mA
Peak total input current (all inputs)
±30 mA
TLC1542C, TLC1543C
0
°C to 70°C
TLC1542I, TLC1543I
-40
°C to 85°C
TA
Operating free-air temperature range
TLC1542Q, TLC1543Q
-40
°C to 125°C
TLC1542M
-55
°C to 125°C
Tstg
Storage temperature range,
-65
°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds
260
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).
MIN
NOM
MAX
UNIT
VCC
Supply voltage
4.5
5
5.5
V
Vref+, see(1)
Positive reference voltage
VCC
V
Vref-, see (1)
Negative reference voltage
0
V
VCC+0.
Vref+-Vref-, see (1)
Differential reference voltage
2.5
VCC
V
2
Analog input voltage ,see (1)
0
VCC
V
VIH
High-level control input voltage
VCC = 4.5 V to 5.5 V
2
V
VIL
Low-level control input voltage
VCC = 4.5 V to 5.5 V
0.8
V
Setup time, address bits at data input before I/O
tsu(A), see Figure 4
100
ns
CLOCK
↑
th(A), see Figure 4
Hold time, address bits after I/O CLOCK
↑
0
ns
th(CS), see Figure 5
Hold time, CS low after last I/O CLOCK
↓
0
ns
tsu(CS), see (2) and
Setup time, CS low before clocking in first
1.425
s
address bit
Clock frequency at I/O CLOCK, see (3)
0
2.1
MHz
twH(I/O)
Pulse duration, I/O CLOCK high,
190
ns
twL(I/O)
Pulse duration, I/O CLOCK low,
190
ns
tt(I/O), see (4) and
Transition time, I/O CLOCK,
1
s
tt(CS)
Transition time, ADDRESS and CS,
10
s
(1)
Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to
REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (Vref+ - Vref-); however, the
electrical specifications are no longer applicable.
(2)
To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock
after CS
↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
(3)
For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (
≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within 9.5
s.
(4)
This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal
room temperature, the devices function with input clock transition time as slow as 1
s for remote data-acquisition applications where
the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
8
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