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參數(shù)資料
| 型號： | 5962-9306001MXA |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, CDIP28 |
| 封裝： | CERAMIC, DIP-28 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 102K |
| 代理商： | 5962-9306001MXA |
AD872A
SMD/883B
REV. B
–3–
Functional Block Diagram and Terminal Assignment
DAC
A/D
DAC
A/D
DAC
A/D
T/H
A/D
443
4
CORRECTION LOGIC
AD872A
+2.5V
REFERENCE
T/H
MSB-BIT 12 (LSB)
*MSB
OTR
*OUTPUT
ENABLE
REF GND
VINA
VINB
AVSS
*DRGND
AGND
CLOCK
REF IN
REF OUT
DVDD DGND
AVDD
*DRVDD
*ONLY AVAILABLE ON 44-PIN SURFACE MOUNT PACKAGE
12
OUTPUT BUFFERS
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44 43 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
NC = NO CONNECT
NC
AVDD
NC
AGND
NC
DRGND
DVDD
DRVDD
CLK
QTR
MSB
NC
AGND
DGND
DRGND
DRVDD
OEN
NC
(MSB) BIT 12
BIT 11
AV
DD
AV
SS
NC
V
INB
V
INA
NC
BIT
10
BIT
9
BIT
8
BIT
7
BIT
5
BIT
4
BIT
3
BIT
2
(MSB)
BIT
1
NC
BIT
6
REF
IN
REF
GND
REF
OUT
AV
SS
AD872A
NC
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD872A
NC = NO CONNECT
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
(LSB) BIT 12
VINA
VINB
AVSS
AVDD
DVDD
DGND
AGND
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSB)
OTR
CLK
REF IN
REF GND
REF OUT
AVSS
DVDD
DGND
AGND
D-28 Package
E-44A Package
tC
tCH
t OD
DATA
IN
DATA
N+1
VIN
CLOCK
BIT 2–12
MSB, OTR
N
N+1
tCL
Figure 1. Timing Diagram
SWITCHING SPECIFICATIONS
(T
MIN to TMAX with AVDD = +5 V, DVDD = +5 V, DRVDD =
+5 V, AV
SS = –5 V; VIL = 0.8 V, VIH = 2.0 V. These characteristics
are included for design guidance only and are not tested or guaranteed.)
Parameter
Symbol
Limits
Units
CLOCK Pulse Width High t
CH
45
ns min
CLOCK Pulse Width Low t
CL
45
ns min
Clock Duty Cycle
40
% min (50% typ)
60
% max
Pipeline Delay (Latency)
3
Clock Cycles
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