參數(shù)資料
型號: 5962-9561328H9C
廠商: AUSTIN SEMICONDUCTOR INC
元件分類: SRAM
英文描述: 512K X 8 STANDARD SRAM, 12 ns, CDFP32
封裝: CERAMIC, DFP-32
文件頁數(shù): 12/17頁
文件大?。?/td> 112K
代理商: 5962-9561328H9C
SRAM
AS5C4008
AS5C4008
Rev. 6.2 06/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55oC<T
A<125
oC or -40oC to +85oC; Vcc = 5V +10%)
MIN
MAX
MIN
MAX
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
READ CYCLE
Read Cycle Time
tRC
12
15
17
20
25
35
45
ns
Address Access Time
tAA
12
15
17
20
25
35
45
ns
Chip Enable Access Time
tACE
12
15
17
20
25
35
45
ns
Output Hold From Address Change
tOH
2
22
2
ns
Chip Enable to Output in Low-Z
tLZCE
2
22
2
ns
4, 6, 7
Chip Disable to Output in High-Z
tHZCE
0
6.5
0
7
0
8080
10
0
15
0
20
ns
4, 6, 7
Output Enable Acess Time
tAOE
78
8
10
12
15
25
ns
Output Enable to Output in Low-Z
tLZOE
0
00
0
ns
4, 6, 7
Output Disable to Output in High-Z
tHZOE
0
6.5
0
7
0
8080
10
0
15
0
20
ns
4, 6, 7
WRITE CYCLE
WRITE Cycle Time
tWC
12
15
17
20
25
35
45
ns
Chip Enable to End of Write
tCW
12
15
16
17
20
30
35
ns
Address Valid to End of Write
tAW
12
15
16
17
20
30
35
ns
Address Setup Time
tAS
0
00
0
ns
Address Hold From End of Write
tAH
1
0
11
1
ns
WRITE Pulse Width
tWP
12
15
16
17
20
30
35
ns
Data Setup Time
tDS
6.5
7
9
10
12
20
25
ns
Data Hold Time
tDH
0
00
0
ns
Write Disable to Output in Low-Z
tLZWE
0
00
0
ns
4, 6, 7
Write Enable to Output in High-Z
tHZWE
0
6.5
0
7
0
8080
10
0
25
0
30
ns
4, 6, 7
-12
UNITS NOTES
SYM
DESCRIPTION
-25
-20
-35
-45
-17
-15
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