參數(shù)資料
型號: 5962-9957701NXD
廠商: TEXAS INSTRUMENTS INC
元件分類: ADC
英文描述: 4-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO32
封裝: GREEN, PLASTIC, TSSOP-32
文件頁數(shù): 25/43頁
文件大?。?/td> 426K
代理商: 5962-9957701NXD
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
31
Write Timing (using R/W, CS0-controlled)
Figure 37 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.
The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0, CS1, and R/W, which becomes valid.
90%
10%
tw(CS)
tsu(R/W)
th(R/W)
CS0
CS1
WR
RD
D(0–11)
DATA_AV
10%
tsu
th
Figure 37. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (RD-controlled)
PARAMETER
MIN
TYP
MAX
UNIT
tsu(R/W)
Setup time, R/W stable to last CS valid
0
ns
tsu
Setup time, data valid to first CS invalid
5
ns
th
Hold time, first CS invalid to data invalid
2
ns
th(R/W)
Hold time, first CS invalid to R/W change
5
ns
tw(CS)
Pulse duration, CS active
10
ns
INTERFACING THE THS1206 TO THE TMS320C30/31/33 DSP
The following application circuit shows an interface of the THS1206 to the TMS320C30/31/33 DSPs. The read and write
timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
CS0
CS1
R/W
DATA_AV
CONV_CLK
DATA
RD
DVDD
THS1206
TMS320C30/31/33
STRB
A23
R/W
INTX
TOUT
DATA
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