
68HC(9)12DG128 Rev 1.0
MOTOROLA
I/O Ports With Key Wake-Up
131
I/O Ports With Key Wake-Up
I/O Ports With Key Wake-Up
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Key Wake-up and Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
Introduction
The 68HC(9)12DG128 offers 16 additional I/O ports with key wake-up
capability.
The key wake-up feature of the 68HC(9)12DG128 issues an interrupt
that will wake up the CPU when it is in the STOP or WAIT mode. Two
ports are associated with the key wake-up function: port H and port J.
Port H and port J wake-ups are triggered with a rising or falling signal
edge. For each pin which has an interrupt enabled, there is a path to the
interrupt request signal which has no clocked devices when the part is in
stop mode. This allows an active edge to bring the part out of stop.
Digital filtering is included to prevent pulses shorter than a specified
value from waking the part from STOP.
An interrupt is generated when a bit in the KWIFH or KWIFJ register and
its corresponding KWIEH or KWIEJ bit are both set. All 16 bits/pins
share the same interrupt vector. Key wake-ups can be used with the pins
configured as inputs or outputs.
Default register addresses, as established after reset, are indicated in
the following descriptions. For information on re-mapping the register
block, refer to
Operating Modes
.
1-kwu