Clock Functions
68HC912DG128 Rev 1.0
146
Clock Functions
MOTOROLA
Clock Loss during
Normal Operation
The no limp-home mode bit, NOLHM, determines how the MCU
responds to an external clock loss in the first case. When the NOLHM bit
is set, with CME or FCME set, and a loss of clock is detected by the clock
monitor circuit, the MCU resets. This is the same behavior as standard
M68HC12 circuits without PLL or operation with VDDPLL at VSS level.
When the NOLHM bit is cleared with CME or FCME set, and a loss of
clock is detected by the clock monitor circuit, the PLL VCO clock at its
minimum frequency is provided as the system clock, allowing the MCU
to continue operating. An MCU using the forced minimum VCO clock as
the system clock is said to be operating in “l(fā)imp-home” mode. In
limp-home mode, PLLON and BCSP outputs are forced high and MCS
is forced low. XCLK, BCLK and MCLK are forced to be PCLK, which is
supplied by the VCO. The LHOME flag in the PLLFLG register indicates
that the MCU is running in limp-home mode. A change of this flag sets
the limp-home interrupt flag and if enabled by the LHIE bit, the
limp-home mode interrupt is requested.
Figure 15 Clock Loss during Normal Operation
Each time the 13-stage counter reaches a count of 4096 XCLK cycles,
a check of the clock monitor status is performed. When the presence of
an external clock is detected, the MCU leaves limp-home mode and the
0 --> 4096
Limp-Home
(Clocked by XCLK)
BCSP
Restore BCSP
SYSCLK
PLLCLK (Limp-Home)
Restore PLLCLK or EXTALi
EXTALi
13-stage counter
Clock Monitor Fail
0 --> 4096
A
B
8-clock