
6
68HC16 Module
2
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The 68HC16 uses a phase-locked loop (PLL) to set its
bus speed. Crystal Y1 is a 32.768kHz frequency refer-
ence. The internal oscillator runs 256 times faster than the
external crystal. When the 68HC16 is reset, it waits for the
PLL to lock before it executes any software. After the PLL
locks onto the reference frequency, the software doubles
the clock speed by writing to the clock synthesizer con-
trol register, selecting a bus speed of 16.78MHz.
U5, the user RAM area, is a 32kbyte CMOS static RAM.
The 74HCT245 octal buffer lets the 68HC16 module
access an 8-bit port on the 40-pin interface connector.
This memory-mapped port consists of separate read
and write strobes, four chip selects, four address LSBs,
and eight data bits.
Serial Communications
J3 is an RS-232 serial port, designed to be compatible
with the IBM PC 9-pin serial port. Use a straight-
through DB9 male-to-female cable to connect J3 to this
port. If the only available serial port has a 25-pin con-
nector, you may use a standard 25-pin to 9-pin
adapter. Table 1 shows the pinout of J3.
The MAX233 is an RS-232 interface voltage level shifter
with two transmitters and two receivers. It includes a
built-in charge pump with internal capacitors that gener-
ates the output voltages necessary to drive RS-232 lines.
40-Pin Data Connector J1
The 20 x 2 pin header connects the 68HC16 module to
a Maxim EV kit. Table 2 lists the function of each pin.
Note that 68HC16 object code is not compatible with
68HC11 object code. Use the 68HC16 module only
with those modules that are designed to support it, and
only download code that is targeted for the 68HC16
module. Downloading incorrect object code into the
68HC16 module will have unpredictable results.
Address Ranges
The 68HC16 μC generates various enable signals for dif-
ferent address ranges. The ROM and RAM enable sig-
nals are fed directly to the respective chips. Several
additional signals (J1.11–J1.14) are available on the data
connector to be used by Maxim EV kits. Table 3 outlines
the address ranges for each of the elements found on
the 68HC16 module, and Table 4 is a truth table that
describes the logic for each of the 68HC16’s chip-select
outputs. Because the addresses are not completely
decoded, the boot ROM and user RAM have shadows.
Unused
None
9
Handshake; hard-wired to RTS
CTS
8
Handshake; hard-wired to CTS
RTS
7
Handshake; hard-wired to DCD and DTR
DSR
6
Signal ground connection
GND
5
Handshake; hard-wired to DCD and DSR
DTR
4
RS-232-compatible data input to
68HC16 module
TXD
3
Handshake; hard-wired to DTR and DSR
RS-232-compatible data output from
68HC16 module
DCD
1
FUNCTION
NAME
PIN
RXD
2
Table 1. Serial Communications Port J3
Table 2. 40-Pin Data-Connector Signals
General I/O port bit 7
QSPI master-in, slave-out
IC4
MISO
34
35
General I/O port bit 0 (LSB)
General I/O port bit 1
General I/O port bit 2
General I/O port bit 3
General I/O port bit 4
General I/O port bit 5
General I/O port bit 6
IC1
IC2
IC3
OC1
OC2
OC3
OC4
27
28
29
30
31
32
33
Buffered data bus bits 1–7
EXTD1–7
20–26
Buffered data bus 0 (LSB)
EXTD0
19
Ground
Unregulated input voltage
+5V from on-board regulator
GND
1–4
5, 6
7, 8
FUNCTION
NAME
PIN
VPREREG
VCC
Read strobe
Write strobe
RD
WR
9
10
Chip select for 7E000–7E7FF
Chip select for 7E800–7EFFF
7E000
7E800
11
12
Chip select for 7F000–7F7FF
Chip select for 7F800–7FFFF
7F000
7F800
13
14
Address bit 0 (LSB)
Address bit 1
Address bit 2
Address bit 3
A00
A01
A02
A03
15
16
17
18
Pulse-width-modulator output
PWMA
40
QSPI chip-select output
System clock output
PCS0/SS
CLKOUT
38
39
QSPI serial clock
SCK
37
QSPI master-out, slave-in
MOSI
36