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參數(shù)資料
| 型號(hào)： | 68HC68W1 |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Serial Digital Pulse Width Modulator |
| 中文描述： | 的CMOS串行數(shù)字脈寬調(diào)制器 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 43K |
| 代理商： | 68HC68W1 |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
March 1998
CDP68HC68W1
CMOS Serial Digital Pulse Width Modulator
Features
Programmable Frequency and Duty Cycle Output
Serial Bus Input; Compatible with Motorola/Intersil
SPI Bus, Simple Shift-Register Type Interface
8 Lead PDIP Package
Schmitt Trigger Clock Input
4V to 6V Operation, -40
o
C to 85
o
C Temperature Range
8MHz Clock Input Frequency
Pinout
CDP68HC68W1
(PDIP)
TOP VIEW
Description
The CDP68HC68W1 modulates a clock input to supply a
variable frequency and duty-cycle output signal. Three 8-bit
registers (pulse width, frequency and control) are accessed
serially after power is applied to initialize device operation.
The value in the pulse width register selects the high
duration of the output period. The frequency register byte
divides the clock input frequency and determines the overall
output clock period. The input clock can be further divided by
two or a low power mode may be selected by the lower two
bits in the control register. A comparator circuit allows
threshold control by setting the output low if the input at the
V
T
pin rises above 0.75V. The CDP68HC68W1 is supplied in
an 8 lead PDIP package (E suffix).
Block Diagram
CLK
CS
V
T
V
SS
1
2
3
4
8
7
6
5
V
DD
PWM
SCK
DATA
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
PKG.
NO.
CDP68HC68W1E
-40 to 85
8 Ld PDIP
E8.3
8 - STAGE RIPPLE
COUNTER
PULSE - WIDTH
DATA REGISTER
8 - STAGE SHIFT
REGISTER
DATA
V
T
V
T
COMPARATOR
INPUT CLK
MODULATOR
LOGIC
8 - STAGE RIPPLE
COUNTER
FREQUENCY
DATA REGISTER
8 - STAGE SHIFT
REGISTER
5 - STAGE 24 - STATE
COMPARATOR
CONTROL REGISTER
2 - STAGE SHIFT
LOAD
LOAD
SCK
CLK
PWM
24
16
8
CS
LOAD
RESET
File Number
1919.3
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