68HC(9)12DG128 Rev 1.0
MOTOROLA
Resets and Interrupts
119
Resets and Interrupts
Resets and Interrupts
Contents
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Maskable interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
Interrupt Control and Priority Registers. . . . . . . . . . . . . . . . . . . . . . .121
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Effects of Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Important User Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Introduction
CPU12 exceptions include resets and interrupts. Each exception has an
associated 16-bit vector, which points to the memory location where the
routine that handles the exception is located. Vectors are stored in the
upper 128 bytes of the standard 64K byte address map.
The six highest vector addresses are used for resets and non-maskable
interrupt sources. The remainder of the vectors are used for maskable
interrupts, and all must be initialized to point to the address of the
appropriate service routine.
Exception Priority
A hardware priority hierarchy determines which reset or interrupt is
serviced first when simultaneous requests are made. Six sources are not
maskable. The remaining sources are maskable, and any one of them
can be given priority over other maskable interrupts.
1-reset