參數(shù)資料
型號(hào): NS7520B-1-C55
廠商: Digi International
文件頁數(shù): 19/68頁
文件大?。?/td> 0K
描述: IC ARM MICROPROCESSOR 177BGA
標(biāo)準(zhǔn)包裝: 160
系列: NET+ARM®
應(yīng)用: 網(wǎng)絡(luò)處理器
核心處理器: ARM7
程序存儲(chǔ)器類型: 外部程序存儲(chǔ)器
RAM 容量: 外部
接口: EBI/EMI,以太網(wǎng),DMA,SPI,UART
輸入/輸出數(shù): 16
電源電壓: 1.4 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 177-LFBGA
包裝: 托盤
供應(yīng)商設(shè)備封裝: 177-BGA(13x13)
NS75 20 b ootstra p ini t i a li zation
22
NS 75 20 Da ta shee t
03 /2 00 6
NS7520 bootstrap initialization
Many internal NS7520 features are configured when the RESET pin is asserted. The address bus
configures the appropriate control register bits at powerup. This table shows which bits control
which functions:
JTAG
The NS7520 provides full support for 1149.1 JTAG boundary scan testing. All NS7520 pins can be
controlled using the JTAG interface port. The JTAG interface provides access to the ARM7TDMI
debug module when the appropriate combination of PLLTST_, BISTEN_, and SCANEN_ is selected (as
ARM Debug
The ARM7TDMI core uses a JTAG TAP controller that shares the pins with the TAP controller used for
1149.1 JTAG boundary scan testing. To enable the ARM7TDMI TAP controller,
{PLLTST_,BISTEN_,SCANEN_}
must be set as shown in Table 3: "NS7520 test modes".
Address bit
Name
Description
ADDR[27]
Endian configuration
0 Little Endian configuration
1 Big Endian configuration
ADDR[26]
CPU bootstrap
0 CPU disabled; GEN_BUSER=1
1 CPU enabled; GEN_BUSER=0
ADDR[24:23]
CS0/MMCR[19:18] setting
00
8-bit SRAM, 63 wait-states/b00
01
32-bit SRAM, 63 wait-states/b01
10
32-bit SRAM
11
16-bit SRAM, 63 wait-states/b11
ADDR[19:9]
GEN_ID setting
GEN_ID=A[19:09],default=’h3ff
ADDR[8:7]
PLL IS setting
IS=A[8:7], default=’b10
ADDR[6:5]
PLL FS setting
FS=A[6:5], default=’b00
ADDR[4:0]
PLL ND setting
ND=A[4:0], default=’b01011
Table 3: NS7520 test modes
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NS7520B-1-I46 IC ARM MICROPROCESSOR 177BGA
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