參數(shù)資料
型號(hào): NS7520B-1-C55
廠商: Digi International
文件頁(yè)數(shù): 8/68頁(yè)
文件大小: 0K
描述: IC ARM MICROPROCESSOR 177BGA
標(biāo)準(zhǔn)包裝: 160
系列: NET+ARM®
應(yīng)用: 網(wǎng)絡(luò)處理器
核心處理器: ARM7
程序存儲(chǔ)器類(lèi)型: 外部程序存儲(chǔ)器
RAM 容量: 外部
接口: EBI/EMI,以太網(wǎng),DMA,SPI,UART
輸入/輸出數(shù): 16
電源電壓: 1.4 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 177-LFBGA
包裝: 托盤(pán)
供應(yīng)商設(shè)備封裝: 177-BGA(13x13)
E t h e rn et interfac e MAC
12
NS 75 20 Da ta shee t
03 /2 00 6
Mnemonic Signal
Description
MDC
MII management clock
Provides the clock for the MDIO serial data channel. The MDC signal
is an NS7520 output. The frequency is derived from the system
operating frequency per the CLKS field setting (see the CLKS field in
MDIO
Management data IO
A bi-directional signal that provides a serial data channel between the
NS7520 and the external Ethernet PHY module.
TXCLK
Transmit clock
An input to the NS7520 from the external PHY module. TXCLK
provides the synchronous data clock for transmit data.
TXD3
TXD2
TXD1
TXD0
Transmit data signals
Nibble bus used by the NS7520 to drive data to the external Ethernet
PHY. All transmit data signals are synchronized to TXCLK.
In ENDEC mode, only TXD0 is used for transmit data.
TXER
Transmit coding error
Output asserted by the NS7520 when an error has occurred in the
transmit data stream.
TXEN
Transmit enable
Asserted when the NS7520 drives valid data on the TXD outputs.
This signal is synchronized to TXCLK.
COL
Transmit collision
Input signal asserted by the external Ethernet PHY when a collision
is detected.
CRS
Receive carrier sense
Asserted by the external Ethernet PHY whenever the receive medium
is non-idle.
RXCLK
Receive clock
An input to the NS7520 from the external PHY module. The receive
clock provides the synchronous data clock for receive data.
RXD3
RXD2
RXD1
RXD0
Receive data signals
Nibble bus used by the NS7520 to input receive data from the
external Ethernet PHY. All receive data signals are synchronized to
RXCLK.
In ENDEC mode, only RXD0 is used for receive data.
RXER
Receive error
Input asserted by the external Ethernet PHY when the Ethernet PHY
encounters invalid symbols from the network.
RXDV
Receive data valid
Input asserted by the external Ethernet PHY when the PHY drives
valid data on the RXD inputs.
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NS7520B-1-I46 IC ARM MICROPROCESSOR 177BGA
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