參數(shù)資料
型號: NS7520B-1-C55
廠商: Digi International
文件頁數(shù): 15/68頁
文件大?。?/td> 0K
描述: IC ARM MICROPROCESSOR 177BGA
標準包裝: 160
系列: NET+ARM®
應用: 網(wǎng)絡處理器
核心處理器: ARM7
程序存儲器類型: 外部程序存儲器
RAM 容量: 外部
接口: EBI/EMI,以太網(wǎng),DMA,SPI,UART
輸入/輸出數(shù): 16
電源電壓: 1.4 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 177-LFBGA
包裝: 托盤
供應商設備封裝: 177-BGA(13x13)
NS 75 20 mo dul es
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NS 75 20 Da ta shee t
03 /2 00 6
NS7520 modules
CPU module
The CPU uses an ARM7TDMI core processor. The ARM architecture is based on Reduced Instruction
Set Computer (RISC) principles, which result in high instruction throughput and impressive real-
time interrupt response for a small, cost-effective circuit. For more information about ARM7TDMI,
see the ARM7TDMI Data Sheet from ARM Ltd. (www.arm.com).
GEN module
The GEN module provides the NS7520 with its main system control functions, as well as these
features:
Two programmable timers with interrupt
One programmable bus-error timer
One programmable watchdog timer
Two 8-bit programmable general-purpose I/O ports
System (SYS) module
The system module provides the system clock (SYS_CLK) and system reset (SYS_RESET) resources.
The system control signals determine the basic operation of the chip:
Signal mnemonic
Signal name
Description
{XTALA1, XTALA2}
Clock source
Operate in one of two ways:
The signals are affixed with a 10-20 MHz parallel mode
quartz crystal or crystal oscillator and the appropriate
components per the component manufacturer.
XTALA1 is driven with a clock signal and XTALA2 is
left open.
{PLLVDD, PLLVSS}
PLL power
Provide an isolated power supply for the PLL.
RESET_
Chip reset
Active low signal asserted to initiate a hardware reset of the
chip.
{TDI, TDO, TNS,
TRST_, TCK}
JTAG interface
Provide a JTAG interface for the chip. This interface is used
for both boundary scan and ICE control of the internal
processor.
{PLLTEST_, BISTEN_,
SCANEN_}
Chip mode
Encoded to determine the chip mode.
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