參數(shù)資料
型號(hào): 70V3319S166BFG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): SRAM
英文描述: 256K X 18 DUAL-PORT SRAM, 3.6 ns, CBGA208
封裝: 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208
文件頁(yè)數(shù): 1/23頁(yè)
文件大?。?/td> 222K
代理商: 70V3319S166BFG
2009 Integrated Device Technology, Inc.
JANUARY 2009
DSC 5623/9
1
Functional Block Diagram
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
– Due to limited pin count PL/
FT option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (6Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, single 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
Grid Array
Supports JTAG features compliant to IEEE 1149.1
– Due to limited pin count, JTAG is not supported on the
128-pin TQFP package
Green parts available, see ordering information
HIGH-SPEED 3.3V
256/128K x 18
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3319/99S
Dout0-8_L
B
W
0
L
B
W
1
L
Din_L
OEL
UBL
LBL
R/
WL
CE0L
CE1L
ab
FT/PIPEL
0/1
1b 0b 1a 0a
1
0
1/0
0b 1b
0a 1a
ab
FT/PIPEL
1/0
REPEATR
A17R(1)
A0R
CNTENR
ADSR
Dout0-8_R
Dout9-17_R
I/O0R -I/O17R
Din_R
ADDR_R
OER
UBR
LBR
R/
WR
CE0R
CE1R
FT/PIPER
CLKR
,
Counter/
Address
Reg.
B
W
1
R
B
W
0
R
FT/PIPER
Counter/
Address
Reg.
CNTENL
ADSL
REPEATL
Dout9-17_L
I/O0L -I/O17L
A17L(1)
A0L
ADDR_L
5623 tbl 01
256K x 18
MEMORY
ARRAY
CLKL
,
JTAG
TCK
TRST
TMS
TDO
TDI
ba
0/1
0b 1b
0a 1a
1
0
1/0
1b 0b
1a 0a
a
b
1/0
NOTE:
1. A17 is a NC for IDT70V3399.
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