- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄298480 > 70V3319S166BFG (INTEGRATED DEVICE TECHNOLOGY INC) 256K X 18 DUAL-PORT SRAM, 3.6 ns, CBGA208 PDF資料下載
參數(shù)資料
| 型號： | 70V3319S166BFG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 DUAL-PORT SRAM, 3.6 ns, CBGA208 |
| 封裝： | 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208 |
| 文件頁數(shù)： | 4/23頁 |
| 文件大?。?/td> | 222K |
| 代理商： | 70V3319S166BFG |
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
12
An
An + 1
An + 2
An + 3
tCYC2
tCH2
tCL2
R/W
ADDRESS
CE0
CLK
CE1
UB, LB
(3)
DATAOUT
OE
tCD2
tCKLZ
Qn
Qn + 1
Qn + 2
tOHZ
tOLZ
tOE
5623 drw 06
(1)
tSC
tHC
tSB
tHB
tSW
tHW
tSA
tHA
tDC
tSC
tHC
tSB
tHB
(4)
(1 Latency)
(5)
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
NOTES:
1.
OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2.
ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by
CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since
ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If
UB, LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
An
An + 1
An + 2
An + 3
tCYC1
tCH1
tCL1
R/W
ADDRESS
DATAOUT
CE0
CLK
OE
tSC
tHC
tCD1
tCKLZ
Qn
Qn + 1
Qn + 2
tOHZ
tOLZ
tOE
tCKHZ
5623 drw 07
(5)
(1)
CE1
UB, LB
(3)
tSB
tHB
tSW
tHW
tSA
tHA
tDC
(4)
tSC
tHC
tSB
tHB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 70V3319S133BCGI | 256K X 18 DUAL-PORT SRAM, 4.2 ns, CBGA256 |
| 70V9389L9PRFI8 | 64K X 18 DUAL-PORT SRAM, 20 ns, PQFP128 |
| IDT70V9289L9PRF8 | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP128 |
| 710026-3 | 25 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
| 710027-5 | 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 70V3319S166BFG8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 208FPBGA - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
| 70V3319S166PRF | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V3319S166PRF8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 128TQFP - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
| 70V3319S166PRFG | 功能描述:靜態(tài)隨機(jī)存取存儲器 256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM RoHS:否 制造商:Cypress Semiconductor 存儲容量:16 Mbit 組織:1 M x 16 訪問時(shí)間:55 ns 電源電壓-最大:3.6 V 電源電壓-最小:2.2 V 最大工作電流:22 uA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TSOP-48 封裝:Tray |
| 70V3319S166PRFG8 | 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 3.3V 4.5M-Bit 256K x 18 12ns/3.6ns 128-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 3.3V 4MBIT 256KX18 12NS/3.6NS 128TQFP - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:256Kx18 STD-PWR 3.3V SYNC DUAL-PORT RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。