參數(shù)資料
型號(hào)： 71M6543GH-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 14/157頁
文件大?。?/td> 2178K
代理商： 71M6543GH-IGT/F
71M6543F/H and 71M6543G/GH Data Sheet
110
2008–2011 Teridian Semiconductor Corporation
v1.2
Name
Location Rst Wk Dir
Description
LCD_DAC[4:0]
240D[4:0]
0
–
R/W
The LCD contrast DAC. This DAC controls the VLCD voltage and has an output range of
2.65 V to 5.3 V. The VLCD voltage is
VLCD = 2.65 + 2.65 * LCD_DAC[4:0]/31
Thus, the LSB of the DAC is 85.5 mV. The maximum DAC output voltage is limited by
V3P3SYS, VBAT, and whether LCD_BSTE = 1.
LCD_E
2400[7]
0
–
R/W
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are ground as are
the COM and SEG outputs if their LCD_MAP bit is 1.
LCD_MAP[55:48]
LCD_MAP[47:40]
LCD_MAP[39:32]
LCD_MAP[31:24]
LCD_MAP[23:16]
LCD_MAP[15:8]
LCD_MAP[7:0]
2405[7:0]
2406[7:0]
2407[7:0]
2408[7:0]
2409[7:0]
240A[7:0]
240B[7:0]
0
–
R/W
Enables LCD segment driver mode of combined SEGDIO pins. Pins that cannot be
configured as outputs (SEG48 through SEG50) become inputs with internal pull ups
when their LCD_MAP bit is zero. Also, note that SEG48 through SEG50 are multiplexed
with the in-circuit emulator signals. When the ICE_E pin is high, the ICE interface is
enabled, and SEG48 through SEG50 become E_RXTX, E_TCLK and E_RST,
respectively.
LCD_MODE[2:0]
2400[6:4]
0
–
R/W
Selects the LCD bias and multiplex mode.
LCD_MODE
Output
000
4 states, 1/3 bias
001
3 states, 1/3 bias
010
2 states, 1/2 bias
011
3 states, 1/2 bias
100
Static display
101
5 states, 1/3 bias
110
6 states, 1/3 bias
LCD_ON
LCD_BLANK
240C[0]
240C[1]
0
–
R/W
Turns on or off all LCD segments without changing LCD data. If both bits are set, the
LCD display is turned on.
LCD_ONLY
28B2[6]
0
W
Puts the 71M6543 to sleep, but with LCD display still active. Ignored if system power is
present. It awakens when the Wake Timer times out, when certain DIO pins are raised,
or when system power returns (see 3.2 Battery Modes).
LCD_RST
240C[2]
0
–
R/W
Clear all bits of LCD data. These bits affect SEGDIO pins that are configured as LCD
drivers. This bit does not auto clear.
LCD_SEG0[5:0]
to
LCD_SEG15[5:0]
2410[5:0] to
241F[5:0]
0
–
R/W
SEG Data for SEG0 through SEG15. DIO data for these pins is in SFR space.
LCD_SEGDIO16[5:0]
to
LCD_SEGDIO45[5:0]
2420[5:0] to
243D[5:0]
0
–
R/W
SEG and DIO data for SEGDIO16 through SEGDIO45. If configured as DIO, bit 1 is
direction (1 is output, 0 is input), bit 0 is data, and the other bits are ignored.
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