參數(shù)資料
型號： 71M6543GH-IGT/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 80/157頁
文件大?。?/td> 2178K
代理商： 71M6543GH-IGT/F
71M6543F/H and 71M6543G/GH Data Sheet
v1.2
2008–2011 Teridian Semiconductor Corporation
29
Figure 10: Samples from Multiplexer Cycle (Frame)
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each
multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.
Figure 11: Accumulation Interval
Figure 11 shows the accumulation interval resulting from SUM_SAMPS[12:0] = 1819 (I/O RAM 0x2107[4:0]
and 0x2108[7:0]), consisting of 1819 samples of 457.8 s each, followed by the XFER_BUSY interrupt.
The sampling in this example is applied to a 50 Hz signal. There is no correlation between the line signal
frequency and the choice of SUM_SAMPS[12:0]. Furthermore, sampling does not have to start when the
line voltage crosses the zero line, and the length of the accumulation interval need not be an integer
multiple of the signal cycles.
MUX
STATE
CK32
(32768 Hz)
0
3
1
2
MUX_DIV = 7 Conversions
Settle
Multiplexer Frame (15 x 30.518 s = 457.8 s)
S
IA
VA
IB
30.5 s
61.04 s
VB
61.04 s
IC
VC
4
5
6
61.04 s
ID
XFER_BUSY
Interrupt to MPU
20ms
833ms
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