參數(shù)資料
型號： 71M6543GH-IGTR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： LEAD FREE, LQFP-100
文件頁數(shù)： 95/157頁
文件大小： 2178K
代理商： 71M6543GH-IGTR/F
71M6543F/H and 71M6543G/GH Data Sheet
42
2008–2011 Teridian Semiconductor Corporation
v1.2
Table 30: The T2CON Bit Functions (SFR 0xC8)
Bit
Symbol
Function
T2CON[7]
–
Not used.
T2CON[6]
I3FR
Polarity control for INT3:
0 = falling edge.
1 = rising edge.
T2CON[5]
I2FR
Polarity control for INT2:
0 = falling edge.
1 = rising edge.
T2CON[4:0]
–
Not used.
Table 31: The IRCON Bit Functions (SFR 0xC0)
Bit
Symbol
Function
IRCON[7]
–
Not used
IRCON[6]
–
Not used
IRCON[5]
IEX6
1 = External interrupt 6 occurred and has not been cleared.
IRCON[4]
IEX5
1 = External interrupt 5 occurred and has not been cleared.
IRCON[3]
IEX4
1 = External interrupt 4 occurred and has not been cleared.
IRCON[2]
IEX3
1 = External interrupt 3 occurred and has not been cleared.
IRCON[1]
IEX2
1 = External interrupt 2 occurred and has not been cleared.
IRCON[0]
–
Not used.
TF0 and TF1 (Timer 0 and Timer 1 overflow flags) is automatically cleared by hardware when the
service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service
routine is called).
External MPU Interrupts
The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in
other parts of the 71M6543, for example the CE, DIO, RTC, or EEPROM interface.
The external interrupts are connected as shown in Table 32. The polarity of interrupts 2 and 3 is
programmable in the MPU via the I3FR and I2FR bits in T2CON (SFR 0xC8). Interrupts 2 and 3 should
be programmed for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that
interrupts 4 through 6 are defined as rising-edge sensitive. Thus, the hardware signals attached to
interrupts 5 and 6 are inverted to achieve the edge polarity shown in Table 32.
Table 32: External MPU Interrupts
External
Interrupt
Connection
Polarity
Flag Reset
0
Digital I/O
see 2.5.10
automatic
1
Digital I/O
see 2.5.10
automatic
2
CE_PULSE
rising
automatic
3
CE_BUSY
falling
automatic
4
VSTAT (VSTAT[2:0] changed)
rising
automatic
5
EEPROM busy (falling), SPI (rising)
automatic
6
XFER_BUSY (falling), RTC_1SEC, RTC_1MIN, RTC_T
falling
manual
External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See 2.5.10
Digital I/O for more information.
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