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參數(shù)資料
| 型號： | 71V433S11PF |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs |
| 中文描述： | 32K的× 32 3.3同步SRAM的流量通過輸出 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大?。?/td> | 261K |
| 代理商： | 71V433S11PF |
6.42
IDT71V433
32K x 32, 3.3V Synchronous SRAM with Flow-Through Outputs Commercial and Industrial Temperature Ranges
Synchronous Write Function Truth Table
(1)
Linear Burst Sequence Table (
LBO
=V
SS
)
Interleaved Burst Sequence Table (
LBO
=V
DD
)
Asynchronous Truth Table
(1)
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2. Multiple bytes may be selected during the same cycle.
Operation
GW
BWE
BW
1
BW
2
BW
3
BW
4
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write all Bytes
L
X
X
X
X
X
Write all Bytes
H
L
L
L
L
L
Write Byte 1
(2)
H
L
L
H
H
H
Write Byte 2
(2)
H
L
H
L
H
H
Write Byte 3
(2)
H
L
H
H
L
H
Write Byte 4
(2)
H
L
H
H
H
L
3729 tbl 08
NOTES:
1. L = V
IL
, H = V
IH
, X = Dont Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
Operation
OE
ZZ
I/O Status
Power
Read
L
L
Data Out (I/O
0
–I/O
31
)
Active
Read
H
L
High-Z
Active
Write
X
L
High-Z —Data In (I/O
0
–I/O
31
)
Active
Deselected
X
L
High-Z
Standby
Sleep Mode
X
H
High-Z
Sleep
3729 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
0
0
1
1
1
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address
(1)
1
1
1
0
0
1
0
0
3729 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address
0
0
0
1
1
0
1
1
Second Address
0
1
1
0
1
1
0
0
Third Address
1
0
1
1
0
0
0
1
Fourth Address
(1)
1
1
0
0
0
1
1
0
3729 tbl 11
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相關代理商/技術參數(shù) |
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|---|---|
| 71V433S11PFI | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:32K x 32 3.3V Synchronous SRAM Flow-Through Outputs |
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