參數(shù)資料
型號(hào)： 71V433S12PFI
廠商： Integrated Device Technology, Inc.
英文描述： 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs
中文描述： 32K的× 32 3.3同步SRAM的流量通過(guò)輸出
文件頁(yè)數(shù)： 1/19頁(yè)
文件大?。?/td> 261K
代理商： 71V433S12PFI
1
2000 Integrated Device Technology, Inc.
AUGUST 2001
DSC-3729/04
Pin Description
Features
N
32K x 32 memory configuration
N
Supports high performance system speed:
Commercial and Industrial:
— 11 11ns Clock-to-Data Access (50MHz)
— 12 12ns Clock-to-Data Access (50MHz)
N
LBO
input selects interleaved or linear burst mode
N
Self-timed write cycle with global write control (
GW
), byte
write enable (
BWE
), and byte writes (
BW
x)
N
Power down controlled by ZZ input
N
Single 3.3V power supply (+10/-5%)
N
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
Description
The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAMorga-
nized as 32K x 32 with full support of various processor interfaces
including the Pentium and PowerPC. The flow-through burst archi-
tecture provides cost-effective 2-1-1-1 performance for processors up to
50 MHz.
32K x 32
3.3V Synchronous SRAM
Flow-Through Outputs
IDT71V433
A
0
–A
14
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS
0
,
CS
1
Chips Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW
1
–
BW
4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock Input
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O
0
–I/O
31
Data Input/Output
I/O
Synchronous
V
DD
, V
DDQ
Core and I/O Power Supply (3.3V)
Power
N/A
V
SS
, V
SSQ
Array Ground, I/O Ground
Power
N/A
3729 tbl 01
Pentiumis a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
The IDT71V433 SRAM contains write, data-input, address and
control registers. There are no registers in the data output path (flow-
through architecture). Internal logic allows the SRAM to generate a
self-timed write based upon a decision which can be left until the
extreme end of the write cycle.
The burst mode feature offers the highest level of performance to
the systemdesigner, as the IDT71V433 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address fromthe processor, initiating the
access sequence. The first cycle of output data will flow-through from
the array after a clock-to-data access time delay fromthe rising clock
edge of the same cycle. If burst mode operation is selected (
ADV
=LOW),
the subsequent three cycles of output data will be available to the
user on the next three rising clock edges. The order of these three
addresses will be defined by the internal burst counter and the
LBO
input pin.
The IDT71V433 SRAM utilizes IDT's high-performance 3.3V
CMOS process, and is packaged in a JEDEC Standard 14mmx 20mm
100-pin thin plastic quad flatpack (TQFP).
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