參數(shù)資料
型號(hào)： 72V233L6BCG
廠(chǎng)商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： FIFO
英文描述： 1K X 18 OTHER FIFO, 4 ns, PBGA100
封裝： 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100
文件頁(yè)數(shù)： 26/45頁(yè)
文件大?。?/td> 381K
代理商： 72V233L6BCG
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
WCLK
SEN
SI
4666 drw18
tENH
tENS
LD
tDS
BIT 0
EMPTY OFFSET
BIT X(1)
BIT 0
FULL OFFSET
tENH
tLDH
tDH
tLDH
BIT X(1)
tLDS
NOTES:
1. x9 to x9 mode: X = 9 for the IDT72V223, X = 10 for the IDT72V233, X = 11 for the IDT72V243, X = 12 for the IDT72V253, X = 13 for the IDT72V263, X = 14 for the IDT72V273,
X = 15 for the IDT72V283 and X = 16 for the IDT72V293.
2. All other modes: X = 8 for the IDT72V223, X = 9 for the IDT72V233, X = 10 for the IDT72V243, X = 11 for the IDT72V253, X = 12 for the IDT72V263, X = 13 for the IDT72V273,
X = 14 for the IDT72V283 and X = 15 for the IDT72V293.
tA
tRTS
tENH
4666 drw17
tENS
Wx
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q0 - Qn
tSKEW2
12
1
tPAFS
tHF
tPAES
Wx+1
2
W3
WEN
tENS
W2
(3)
4
5
tENH
W4
W5
(3)
3
W1
tA
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (
OR), will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
IR will be LOW throughout the Retransmit setup procedure.
If x18 Input or x18 Output bus Width is selected, D = 513 for the IDT72V223, 1,025 for the IDT72V233, 2,049 for the IDT72V243, 4,097 for the IDT72V253, 8,193 for the IDT72V263,
16,385 for the IDT72V273, 32,769 for the IDT72V283 and 65,537 for the IDT72V293.
If both x9 Input and x9 Output bus Widths are selected, D = 1,025 for the IDT72V223, 2,049 for the IDT72V233, 4,097 for the IDT72V243, 8,193 for the IDT72V253, 16,385
for the IDT72V263, 32,769 for the IDT72V273, 65,537 for the IDT72V283 and 131,073 for the IDT72V293.
3.
OE = LOW
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during
MRS.
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
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參數(shù)描述
72V233L6PF 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線(xiàn)寬度:18 bit 總線(xiàn)定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪(fǎng)問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
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72V233L7-5BC 功能描述:先進(jìn)先出 RoHS:否 制造商:IDT 電路數(shù)量: 數(shù)據(jù)總線(xiàn)寬度:18 bit 總線(xiàn)定向:Unidirectional 存儲(chǔ)容量:4 Mbit 定時(shí)類(lèi)型:Synchronous 組織:256 K x 18 最大時(shí)鐘頻率:100 MHz 訪(fǎng)問(wèn)時(shí)間:10 ns 電源電壓-最大:3.6 V 電源電壓-最小:6 V 最大工作電流:35 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-80 封裝:
72V233L7-5BCI 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Dual Depth/Width Uni-Dir 1K x 18/2K x 9 100-Pin CABGA 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC DUAL DEPTH/WIDTH UNI-DIR 1KX18/2KX9 100CABGA - Trays
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