參數(shù)資料
型號: 72V233L6BCG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: FIFO
英文描述: 1K X 18 OTHER FIFO, 4 ns, PBGA100
封裝: 11 X 11 MM, 1 MM PITCH, GREEN, BGA-100
文件頁數(shù): 37/45頁
文件大?。?/td> 381K
代理商: 72V233L6BCG
42
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V223/233/243/253/263/273/283/293 3.3V HIGH DENSITY SUPERSYNC IITM NARROW BUS FIFO
512 x 18, 1K x 9/18, 2K x 9/18, 4K x 9/18, 8K x 9/18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9
FEBRUARY 11, 2009
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and
TRST) are provided to
supporttheJTAGboundaryscaninterface.TheIDT72V223/72V233/72V243/
72V253/72V263/72V273/72V283/72V293 incorporates the necessary tap
controller and modified pad cells to implement the JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The Standard JTAG interface consists of four basic elements:
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
The following sections provide a brief description of each element. For a
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
Figure 32. Boundary Scan Architecture
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,
TRST)
and one output port (TDO).
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
T
A
P
TAP
Cont-
roller
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
clkDR, ShiftDR
UpdateDR
TDO
TDI
TMS
TCLK
TRST
clklR, ShiftlR
UpdatelR
Instruction Register
Instruction Decode
Control Signals
4666 drw35
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