參數(shù)資料
型號: 73K222AL-IP
廠商: TDK Corporation
英文描述: V.22, V.21, Bell 212A, 103 Single-Chip Modem
中文描述: .22,.21,貝爾212A章,103單芯片調(diào)制解調(diào)器
文件頁數(shù): 19/28頁
文件大小: 160K
代理商: 73K222AL-IP
73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
19
DYNAMIC CHARACTERISTICS AND TIMING
(continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Guard Tone Generator
550 Hz
Tone Accuracy
1800 Hz
-20
+20
Hz
550 Hz
-4.0
-3.0
-2.0
dB
Tone Level
(Below DPSK Output)
1800 Hz
-7.0
-6.0
-5.0
dB
550 Hz
-50
dB
Harmonic Distortion
700 to 2900 Hz
1800 Hz
-60
dB
Timing
(Refer to Timing Diagrams)
TAL
CS
/Address setup before ALE Low
12
ns
CS
CS
hold after ALE low
0
ns
TLA
ADDR
Address hold after ALE low
10
ns
TLC
ALE Low to
RD
/
WR
Low
10
ns
TCL
RD
/
WR
Control to ALE High
0
ns
TRD
Data out from
RD
Low
0
140
ns
TLL
ALE width
15
ns
TRDF
Data float after
RD
High
50
ns
TRW
RD
width
50
ns
TWW
WR
width
50
ns
TDW
Data setup before
WR
High
15
ns
TWD
Data hold after
WR
High
12
ns
TCKD
Data out after EXCLK Low
200
ns
TCKW
WR
after EXCLK Low
150
ns
TDCK
Data setup before EXCLK Low
150
ns
TAC
Address setup before control*
50
ns
TCA
Address hold after control*
50
ns
TWH
Data Hold after EXCLK
20
* Control for setup is the falling edge of
RD
or
WR
.
Control for hold is the falling edge of
RD
or the rising edge of
WR
.
NOTE:Asserting ALE,
CS
, and
RD
or
WR
concurrently can cause unintentional register accesses. When using
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
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