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參數(shù)資料
| 型號： | 73K222AL-IP |
| 廠商： | TDK Corporation |
| 英文描述： | V.22, V.21, Bell 212A, 103 Single-Chip Modem |
| 中文描述： | .22，.21，貝爾212A章，103單芯片調(diào)制解調(diào)器 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大小： | 160K |
| 代理商： | 73K222AL-IP |
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73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip
6
PIN DESCRIPTION
(continued)
DTE USER
NAME
28-PIN
TYPE
DESCRIPTION
EXCLK
19
I
External Clock. This signal is used in synchronous transmission
when the external timing option has been selected. In the external
timing mode the rising edge of EXCLK is used to strobe synchronous
DPSK transmit data applied to on the TXD pin. Also used for serial
control interface.
RXCLK
23
O
Receive Clock. The falling edge of this clock output is coincident with
the transitions in the serial received data output. The rising edge of
RXCLK can be used to latch the valid output data. RXCLK will be
valid as long as a carrier is present.
RXD
22
O/
Weak
Pull -up
Received Data Output. Serial receive data is available on this pin.
The data is always valid on the rising edge of RXCLK when in
synchronous mode. RXD will output constant marks if no carrier is
detected.
TXCLK
18
O
Transmit Clock. This signal is used in synchronous transmission to
latch serial input data on the TXD pin. Data must be provided so that
valid data is available on the rising edge of the TXCLK. The transmit
clock is derived from different sources depending upon the
synchronization mode selection. In Internal Mode the clock is
generated internally. In External Mode TXCLK is phase locked to the
EXCLK pin. In Slave Mode TXCLK is phase locked to the RXCLK
pin. TXCLK is always active.
TXD
21
I
Transmit Data Input. Serial data for transmission is applied on this pin.
In synchronous modes, the data must be valid on the rising edge of the
TXCLK clock. In asynchronous modes (1200/600 bit/s or 300 baud)
no clocking is necessary. DPSK data must be 1200/600 bit/s +1%,
-2.5% or +2.3%, -2.5 % in extended overspeed mode.
ANALOG INTERFACE AND OSCILLATOR
RXA
27
I
Received modulated analog signal input from the telephone line
interface.
TXA
16
O
Transmit analog output to the telephone line interface.
XTL1
XTL2
2
3
I
I
These pins are for the internal crystal oscillator requiring a 11.0592 MHz
parallel
mode crystal. Load capacitors should be connected from XTL1
and XTL2 to Ground. XTL2 can also be driven from an external clock.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 73K222AU | Single-Chip Modem Modem with UART |
| 73K222AU-IH | Single-Chip Modem Modem with UART |
| 73K222AU-IP | Single-Chip Modem Modem with UART |
| 73K222BL | V.22, V.21, Bell 212A,Bell 103 Single-Chip Modem with Integrated Hybrid(V.22, V.21, Bell 212A,Bell 103,帶混合電路的單片Modem) |
| 73K224BL | V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid(V.22bis/V.22/V.21/Bell 212A/103單片Modem w/ 集成混合電路) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73K222ASL-IP | 制造商:SSI 功能描述:1.2 kbps DATA, MODEM, PDIP22 |
| 73K222AU | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:Single-Chip Modem Modem with UART |
| 73K222AU-IH | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:Single-Chip Modem Modem with UART |
| 73K222AU-IP | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:Single-Chip Modem Modem with UART |
| 73K222BL | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Single-Chip Modem |
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