參數(shù)資料
型號: 73K324L-IGT
廠商: Electronic Theatre Controls, Inc.
英文描述: CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem
中文描述: 國際電話電報諮詢委員會V.22bis,.22,.21,.23,貝爾212A章單芯片調(diào)制解調(diào)器
文件頁數(shù): 22/31頁
文件大?。?/td> 183K
代理商: 73K324L-IGT
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
22
DYNAMIC CHARACTERISTICS AND TIMING
(continued)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
Timing
(Refer to Timing Diagrams)
Parallel Mode:
TAL
CS
/Addr. setup before ALE Low
30
ns
TLA
CS
/Addr. hold after ALE Low
6
ns
TLC
TCL
ALE Low to
RD
/
WR
Low
40
10
ns
ns
RD
/
WR
Control to ALE High
Data out from
RD
Low
TRD
90
ns
TLL
ALE width
25
ns
TRDF
Data float after
RD
High
40
ns
TRW
TWW
RD
width
70
70
ns
ns
WR
width
Data setup before
WR
High
TDW
70
ns
TWD
Data hold after
WR
High
20
ns
Serial Mode:
TRCK
TAR
Clock high after
RD
250
0
T1
ns
ns
Address setup before
RD
low
TRA
Address hold after
RD
low
RD
to data valid
350
ns
TRD
110
ns
TRDF
Data float after
RD
high
50
ns
TCKDR
Read data out after falling edge
of EXCLK
300
ns
TWW
WR
width
350
ns
TAW
Address setup before
WR
Address hold after rising edge of
WR
50
ns
TWA
50
ns
TCKDW
Write data hold after falling edge
of EXCLK
200
ns
TCKW
WR
high after falling edge of
EXCLK
330
T1& T2
ns
TDCK
Data setup before falling edge of
EXCLK
50
ns
T1, T2
Minimum period
500
ns
Note:
T1 and T2 are the low/high periods, respectively, of EXCLK in Serial mode.
NOTE: Asserting ALE,
CS
, and
RD
or
WR
concurrently can cause unintentional register accesses. When using
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
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