參數(shù)資料
型號: 73K324L-IP
廠商: Electronic Theatre Controls, Inc.
英文描述: CCITT V.22bis, V.22, V.21, V.23, Bell 212A Single-Chip Modem
中文描述: 國際電話電報諮詢委員會V.22bis,.22,.21,.23,貝爾212A章單芯片調制解調器
文件頁數(shù): 8/31頁
文件大小: 183K
代理商: 73K324L-IP
73K324L
CCITT V.22bis, V.22, V.21, V.23, Bell 212A
Single-Chip Modem
8
CONTROL REGISTER 0
D7
D6
D5
D4
D3
D2
D1
D0
CR0
000
MODUL.
OPTION
MODUL.
TYPE 1
MODUL.
TYPE 0
TRANSMIT
MODE 2
TRANSMIT
MODE 1
TRANSMIT
MODE 0
TRANSMIT
ENABLE
ANSWER/
ORIGINATE
BIT NO.
NAME
CONDITION
DESCRIPTION
0
Selects Answer mode (transmit in high band, receive in
low band) or in V.23 HDX mode, receive at 1200 bit/s and
transmit at 75 bit/s.
1
Selects Originate mode (transmit in low band,receive in
high band) or in V.23 HDX mode, receive at 75 bit/s and
transmit at 1200 bit/s.
D0
Answer/
Originate
Note: This bit works with Tone Register bits D0 and D6 to
program special tones detected in the Detect Register.
See Detect and Tone Registers.
0
1
Disables transmit output at TXA.
Enables transmit output at TXA.
D1
Transmit
Enable
Note: Transmit Enable must be set to 1 to allow activation
of Answer Tone, DTMF, or Carrier.
D5
D4 D3
D2
0
0
0
0
Selects Power Down mode. All functions are disabled
except the digital interface.
0
0
0
1
Internal Synchronous mode. In this mode TXCLK is an
internally derived 600, 1200 or 2400 Hz signal. Serial
input data appearing at TXD must be valid on the rising
edge of TXCLK. Receive data is clocked out of RXD on
the falling edge of RXCLK.
0
0
1
0
External Synchronous mode. Operation is identical to
internal synchronous, but TXCLK is connected internally
to EXCLK pin, and a 600, 1200 or 2400 Hz clock must be
supplied externally.
0
0
1
1
Slave Synchronous mode. Same operation as other
Synchronous modes. TXCLK is connected internally to
the RXCLK pin in this mode.
0
1
0
0
Selects Asynchronous mode - 8 bits/character (1 start bit,
6 data bits, 1 stop bit).
0
1
0
1
Selects Asynchronous mode - 9 bits/character (1 start bit,
7 data bits, 1 stop bit).
0
1
1
0
Selects Asynchronous mode - 10 bits/character (1 start
bit, 8 data bits, 1 stop bit).
0
1
1
1
Selects Asynchronous mode - 11 bits/character (1 start
bit, 8 data bits, Parity and/or 1 or 2 stop bits).
D5, D4,
D3, D2
Transmit
Mode
1
X
0
0
Selects FSK operation.
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