參數(shù)資料
型號： 73S1209F-68IM/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY MANAGEMENT CKT, QCC68
封裝： LEAD FREE, QFN-68
文件頁數(shù)： 117/123頁
文件大?。?/td> 1385K
代理商： 73S1209F-68IM/F
DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
93
Parity Control Register (SParCtl): 0xFE11
0x00
This register provides the ability to configure the parity circuitry on the smart card interface. The settings
apply to both integrated smart card interfaces.
Table 89: The SParCtl Register
MSB
LSB
–
DISPAR BRKGEN BRKDET RETRAN DISCRX
INSPE
FORCPE
Bit
Symbol
Function
SParCtl.7
–
SParCtl.6
DISPAR
Disable Parity Check – 1 = disabled, 0 = enabled. If enabled, the UART
will check for even parity (the number of 1’s including the parity bit is even)
on every character. This also applies to the TS during ATR.
SParCtl.5
BRKGEN
Break Generation Disable – 1 = disabled, 0 = enabled. If enabled, and T=0
protocol, the UART will generate a Break to the smart card if a parity error
is detected on a receive character. No Break will be generated if parity
checking is disabled. This also applies to TS during ATR.
SParCtl.4
BRKDET
Break Detection Disable – 1 = disabled, 0 = enabled. If enabled, and T=0
protocol, the UART will detect the generation of a Break by the smart card.
SParCtl.3
RETRAN
Retransmit Byte – 1 = enabled, 0 = disabled. If enabled and a Break is
detected from the smart card (Break Detection must be enabled), the last
character will be transmitted again. This bit applies to T=0 protocol.
SParCtl.2
DISCRX
Discard Received Byte – 1 = enabled, 0 = disabled. If enabled and a parity
error is detected (Parity checking must be enabled), the last character
received will be discarded. This bit applies to T=0 protocol.
SParCtl.1
INSPE
Insert Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If
enabled, the UART will insert a parity error in every character transmitted
by generating odd parity instead of even parity for the character.
SParCtl.0
FORCPE
Force Parity Error – 1 = enabled, 0 = disabled. Used for test purposes. If
enabled, the UART will generate a parity error on a character received from
the smart card.
相關PDF資料
PDF描述
73S1209F-68IMR/F POWER SUPPLY MANAGEMENT CKT, QCC68
73S1209F-44IMR/F POWER SUPPLY MANAGEMENT CKT, QCC44
73S1209F-68IMR/F POWER SUPPLY MANAGEMENT CKT, QCC68
73S1209F-68IM/F POWER SUPPLY MANAGEMENT CKT, QCC68
73S1209F-44IMR/F POWER SUPPLY MANAGEMENT CKT, QCC44
相關代理商/技術參數(shù)
參數(shù)描述
73S1209F-68IMR/F 功能描述:8位微控制器 -MCU Contained 80515-SoC Serial Hst Interface RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
73S1209F-68IMR/F/P 功能描述:IC SMART CARD READER PROG 68-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:73S12xx 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:260 系列:73S12xx 核心處理器:80515 芯體尺寸:8-位 速度:24MHz 連通性:I²C，智能卡，UART/USART，USB 外圍設備:LED，POR，WDT 輸入/輸出數(shù):9 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-VFQFN 裸露焊盤 包裝:管件
73S1209F-68M/F/P1 功能描述:8位微控制器 -MCU Contained 80515-SoC Serial Hst Interface RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
73S1209F-EB 功能描述:開發(fā)板和工具包 - 8051 73S1209F Eval Brd (Doc. Cd, Cable) RoHS:否 制造商:Silicon Labs 產品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓:
73S1209F-IM44 DK 制造商:Maxim Integrated Products 功能描述:Development Boards & Kits - 8051 73S1209F Dev Kit Eval Bd Ice Cable Cd
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