參數(shù)資料
型號： 73S1209F-68IM/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 電源管理
英文描述： POWER SUPPLY MANAGEMENT CKT, QCC68
封裝： LEAD FREE, QFN-68
文件頁數(shù)： 33/123頁
文件大?。?/td> 1385K
代理商： 73S1209F-68IM/F
DS_1209F_004
73S1209F Data Sheet
Rev. 1.2
17
Table 5: Security Control Registers
Register
SFR
Address
R/W
Description
FLSHCTL
0xB2
R/W
Bit 0 (FLSH_PWE): Program Write Enable:
0 – MOVX commands refer to XRAM Space, normal operation (default).
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
This bit is automatically reset after each byte written to flash. Writes to this
bit are inhibited when interrupts are enabled.
W
Bit 1 (FLSH_MEEN): Mass Erase Enable:
0 – Mass Erase disabled (default).
1 – Mass Erase enabled.
Must be re-written for each new Mass Erase cycle.
R/W
Bit 6 (SECURE):
Enables security provisions that prevent external reading of flash memory
and CE program RAM. This bit is reset on chip reset and may only be set.
Attempts to write zero are ignored.
TRIMPCtl
0xFFD1
W
0xA6 value will cause the selected fuse to be blown. All other values will
stop the burning process.
FUSECtl
0xFFD2
W
0x54 value will set up for security fuse control. All other values are
reserved and should not be used.
SECReg
0xFFD7
W
Bit 7 (PARAMSEC):
0 – Normal operation
1 – Enable permanent programming of the security fuses.
R
Bit 5 (SECPIN):
Indicates the state of the SEC pin. The SEC pin is held low by a pull-down
resistor. The user can force this pin high during boot sequence time to
indicate to the firmware that sec mode 1 is desired.
R/W
Bit 1 (SECSET1):
See Program Security section.
R/W
Bit 0 (SECSET0):
See Program Security section.
相關(guān)PDF資料
PDF描述
73S1209F-68IMR/F POWER SUPPLY MANAGEMENT CKT, QCC68
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73S1209F-68IMR/F POWER SUPPLY MANAGEMENT CKT, QCC68
73S1209F-68IM/F POWER SUPPLY MANAGEMENT CKT, QCC68
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